cpu: integrate nmigen version of Minerva, add submodule

.gitmodules

@@ -16,3 +16,6 @@
 [submodule "litex/soc/cores/cpu/vexriscv/verilog"]
 	path = litex/soc/cores/cpu/vexriscv/verilog
 	url = https://github.com/enjoy-digital/VexRiscv-verilog.git
+[submodule "litex/soc/cores/cpu/minerva/verilog"]
+	path = litex/soc/cores/cpu/minerva/verilog
+	url = http://github.com/enjoy-digital/minerva-verilog

litex/soc/cores/cpu/minerva/core.py

@@ -9,7 +9,7 @@ class Minerva(Module):
     name = "minerva"
     endianness = "little"
     gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf")
-    gcc_flags = "-D__minerva__ -march=rv32i -mabi=ilp32"
+    gcc_flags = "-march=rv32i -mabi=ilp32" + " -D__minerva__"
     linker_output_format = "elf32-littleriscv"
 
     def __init__(self, platform, cpu_reset_address, variant="standard"):
@@ -19,17 +19,48 @@ class Minerva(Module):
         self.dbus = wishbone.Interface()
         self.interrupt = Signal(32)
 
-        ###
+        # # #
 
-        try: # FIXME: workaround until Minerva code is released
-            from minerva.core import Minerva as MinervaCPU
-            self.submodules.cpu = MinervaCPU(reset_address=cpu_reset_address)
-            self.comb += [
-                self.cpu.reset.eq(self.reset),
-                self.cpu.external_interrupt.eq(self.interrupt),
-                self.cpu.ibus.connect(self.ibus),
-                self.cpu.dbus.connect(self.dbus)
-            ]
-        except:
-            pass
+        self.specials += Instance("minerva_cpu",
+            # clock / reset
+            i_clk=ClockSignal(),
+            i_rst=ResetSignal(),
 
+            # interrupts
+            i_external_interrupt=self.interrupt,
+
+            # ibus
+            o_ibus_stb=self.ibus.stb,
+            o_ibus_cyc=self.ibus.cyc,
+            o_ibus_cti=self.ibus.cti,
+            o_ibus_bte=self.ibus.bte,
+            o_ibus_we=self.ibus.we,
+            o_ibus_adr=self.ibus.adr,
+            o_ibus_dat_w=self.ibus.dat_w,
+            o_ibus_sel=self.ibus.sel,
+            i_ibus_ack=self.ibus.ack,
+            i_ibus_err=self.ibus.err,
+            i_ibus_dat_r=self.ibus.dat_r,
+
+            # dbus
+            o_dbus_stb=self.dbus.stb,
+            o_dbus_cyc=self.dbus.cyc,
+            o_dbus_cti=self.dbus.cti,
+            o_dbus_bte=self.dbus.bte,
+            o_dbus_we=self.dbus.we,
+            o_dbus_adr=self.dbus.adr,
+            o_dbus_dat_w=self.dbus.dat_w,
+            o_dbus_sel=self.dbus.sel,
+            i_dbus_ack=self.dbus.ack,
+            i_dbus_err=self.dbus.err,
+            i_dbus_dat_r=self.dbus.dat_r,
+        )
+
+        # add verilog sources
+        self.add_sources(platform)
+
+    @staticmethod
+    def add_sources(platform):
+        vdir = os.path.join(
+            os.path.abspath(os.path.dirname(__file__)), "verilog")
+        platform.add_source(os.path.join(vdir, "minerva.v"))

litex/soc/cores/cpu/minerva/verilog

@@ -0,0 +1 @@
+Subproject commit 297db8adfed0671afd6114f8ff3c18c9434e4686