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use new direct access on endpoints

This commit is contained in:
Florent Kermarrec 2014-10-16 17:42:24 +02:00
parent 9649b1497c
commit d860813dec
1 changed files with 7 additions and 7 deletions
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14
miscope/uart2wishbone.py
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@ -95,15 +95,15 @@ class UART2Wishbone(Module, AutoCSR):
cmd = Signal(8) cmd = Signal(8)
fsm.act("WAIT_CMD", fsm.act("WAIT_CMD",
If(uart.rx.source.stb, If(uart.rx.source.stb,
If( (uart.rx.source.payload.d == self.WRITE_CMD) | If( (uart.rx.source.d == self.WRITE_CMD) |
(uart.rx.source.payload.d == self.READ_CMD), (uart.rx.source.d == self.READ_CMD),
NextState("RECEIVE_BURST_LENGTH") NextState("RECEIVE_BURST_LENGTH")
), ),
word_cnt.clr.eq(1), word_cnt.clr.eq(1),
burst_cnt.clr.eq(1) burst_cnt.clr.eq(1)
) )
) )
self.sync += If(fsm.ongoing("WAIT_CMD") & uart.rx.source.stb, cmd.eq(uart.rx.source.payload.d)) self.sync += If(fsm.ongoing("WAIT_CMD") & uart.rx.source.stb, cmd.eq(uart.rx.source.d))
#### ####
burst_length = Signal(8) burst_length = Signal(8)
@ -115,7 +115,7 @@ class UART2Wishbone(Module, AutoCSR):
) )
) )
self.sync += \ self.sync += \
If(fsm.ongoing("RECEIVE_BURST_LENGTH") & uart.rx.source.stb, burst_length.eq(uart.rx.source.payload.d)) If(fsm.ongoing("RECEIVE_BURST_LENGTH") & uart.rx.source.stb, burst_length.eq(uart.rx.source.d))
#### ####
address = Signal(32) address = Signal(32)
@ -132,7 +132,7 @@ class UART2Wishbone(Module, AutoCSR):
) )
self.sync += \ self.sync += \
If(fsm.ongoing("RECEIVE_ADDRESS") & uart.rx.source.stb, If(fsm.ongoing("RECEIVE_ADDRESS") & uart.rx.source.stb,
address.eq(Cat(uart.rx.source.payload.d, address[0:24])) address.eq(Cat(uart.rx.source.d, address[0:24]))
) )
### ###
@ -189,13 +189,13 @@ class UART2Wishbone(Module, AutoCSR):
) )
), ),
uart.tx.sink.stb.eq(1), uart.tx.sink.stb.eq(1),
chooser(data, word_cnt.value, uart.tx.sink.payload.d, n=4, reverse=True) chooser(data, word_cnt.value, uart.tx.sink.d, n=4, reverse=True)
) )
### ###
self.sync += \ self.sync += \
If(fsm.ongoing("RECEIVE_DATA") & uart.rx.source.stb, If(fsm.ongoing("RECEIVE_DATA") & uart.rx.source.stb,
data.eq(Cat(uart.rx.source.payload.d, data[0:24])) data.eq(Cat(uart.rx.source.d, data[0:24]))
).Elif(fsm.ongoing("READ_DATA") & self.wishbone.stb & self.wishbone.ack, ).Elif(fsm.ongoing("READ_DATA") & self.wishbone.stb & self.wishbone.ack,
data.eq(self.wishbone.dat_r) data.eq(self.wishbone.dat_r)
) )