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Merge pull request #162 from antmicro/full-conf-vexriscv 

Add full and full_debug CPU variant of VexRiscv
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enjoy-digital 2019-04-17 19:01:55 +02:00 committed by GitHub
parent ce81a39ce9 40de01bcb0
commit d860eeea4f
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2 changed files with 4 additions and 2 deletions
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4
litex/soc/cores/cpu/vexriscv/core.py
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@ -16,7 +16,7 @@ class VexRiscv(Module, AutoCSR):
def __init__(self, platform, cpu_reset_address, variant=None):
variant = "std" if variant is None else variant
variant = "std_debug" if variant == "debug" else variant
variants = ("std", "std_debug", "lite", "lite_debug", "min", "min_debug")
variants = ("std", "std_debug", "lite", "lite_debug", "min", "min_debug", "full", "full_debug")
assert variant in variants, "Unsupported variant %s" % variant
self.platform = platform
self.variant = variant
@ -157,6 +157,8 @@ class VexRiscv(Module, AutoCSR):
"lite_debug": "VexRiscv_LiteDebug.v",
"min": "VexRiscv_Min.v",
"min_debug": "VexRiscv_MinDebug.v",
"full": "VexRiscv_Full.v",
"full_debug": "VexRiscv_FullDebug.v",
}
cpu_filename = verilog_variants[variant]
vdir = os.path.join(os.path.abspath(os.path.dirname(__file__)), "verilog")

2
litex/soc/cores/cpu/vexriscv/verilog

@ -1 +1 @@
Subproject commit d7bbc2c167f1a0886c446d3c305d0ed4388570be
Subproject commit ebe4064653bc143bf92a0ccdd1099173620fcbf5