bank/csrgen: fix RE generation

2012-02-18 18:56:18 +01:00 · 2012-02-18 18:56:18 +01:00 · d8d4e81b6e
parent 55a265d967
commit d8d4e81b6e
1 changed files with 1 additions and 0 deletions
--- a/migen/bank/csrgen.py
+++ b/migen/bank/csrgen.py
@ -27,6 +27,7 @@ class Bank:
 					self.interface.we & \
 					(self.interface.adr[:nbits] == Constant(i, BV(nbits)))))
 			elif isinstance(reg, RegisterFields):
+				sync.append(reg.re.eq(0))
 				bwra = [Constant(i, BV(nbits))]
 				offset = 0
 				for field in reg.fields: