bank/csrgen: fix RE generation
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@ -27,6 +27,7 @@ class Bank:
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self.interface.we & \
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self.interface.we & \
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(self.interface.adr[:nbits] == Constant(i, BV(nbits)))))
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(self.interface.adr[:nbits] == Constant(i, BV(nbits)))))
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elif isinstance(reg, RegisterFields):
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elif isinstance(reg, RegisterFields):
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sync.append(reg.re.eq(0))
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bwra = [Constant(i, BV(nbits))]
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bwra = [Constant(i, BV(nbits))]
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offset = 0
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offset = 0
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for field in reg.fields:
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for field in reg.fields:
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