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cores/jtag/XilinxJTAG: Add support for Zynq UltraScale+ 

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
This commit is contained in:
Sylvain Munaut 2022-03-02 14:12:18 +01:00
parent 4bc1691487
commit d8df6cb27d
1 changed files with 1 additions and 1 deletions
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litex/soc/cores/jtag.py
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@ -308,7 +308,7 @@ class XilinxJTAG(Module):
prim_dict = {
# Primitive Name Ðevice (startswith)
"BSCAN_SPARTAN6" : ["xc6"],
"BSCANE2" : ["xc7", "xcku", "xcvu"],
"BSCANE2" : ["xc7", "xcku", "xcvu", "xczu"],
}
for prim, prim_devs in prim_dict.items():
for prim_dev in prim_devs: