Replace Signal(bits_for(... with Signal(max=...

This commit is contained in:
Sebastien Bourdeauducq 2012-11-29 21:53:36 +01:00
parent 50ed73c937
commit d8e478efee
7 changed files with 10 additions and 13 deletions

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@ -4,8 +4,8 @@ from migen.fhdl import verilog
dx = 5 dx = 5
dy = 5 dy = 5
x = Signal(bits_for(dx-1)) x = Signal(max=dx)
y = Signal(bits_for(dy-1)) y = Signal(max=dy)
out = Signal() out = Signal()
my_2d_array = Array(Array(Signal() for a in range(dx)) for b in range(dy)) my_2d_array = Array(Array(Signal() for a in range(dx)) for b in range(dy))

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@ -33,8 +33,7 @@ class Unpack(Actor):
("source", Source, layout_to)) ("source", Source, layout_to))
def get_fragment(self): def get_fragment(self):
muxbits = bits_for(self.n-1) mux = Signal(max=self.n)
mux = Signal(muxbits)
last = Signal() last = Signal()
comb = [ comb = [
last.eq(mux == (self.n-1)), last.eq(mux == (self.n-1)),
@ -64,8 +63,7 @@ class Pack(Actor):
("source", Source, pack_layout(layout_from, n))) ("source", Source, pack_layout(layout_from, n)))
def get_fragment(self): def get_fragment(self):
demuxbits = bits_for(self.n-1) demux = Signal(max=self.n)
demux = Signal(demuxbits)
load_part = Signal() load_part = Signal()
strobe_all = Signal() strobe_all = Signal()

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@ -15,7 +15,7 @@ class Slot:
self.adr = Signal(aw) self.adr = Signal(aw)
self.time = time self.time = time
if self.time: if self.time:
self._counter = Signal(bits_for(time)) self._counter = Signal(max=time+1)
self.mature = Signal() self.mature = Signal()
self.allocate = Signal() self.allocate = Signal()
@ -76,7 +76,7 @@ class Port:
self.base = base self.base = base
nslots = len(self.slots) nslots = len(self.slots)
if nslots > 1: if nslots > 1:
self.tag_issue = Signal(bits_for(nslots-1)) self.tag_issue = Signal(max=nslots)
self.tag_call = Signal(tagbits) self.tag_call = Signal(tagbits)
def get_call_expression(self, slotn=0): def get_call_expression(self, slotn=0):

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@ -15,7 +15,7 @@ class Divider:
w = self.w w = self.w
qr = Signal(2*w) qr = Signal(2*w)
counter = Signal(bits_for(w)) counter = Signal(max=w+1)
divisor_r = Signal(w) divisor_r = Signal(w)
diff = Signal(w+1) diff = Signal(w+1)

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@ -54,7 +54,7 @@ def chooser(signal, shift, output, n=None, reverse=False):
def timeline(trigger, events): def timeline(trigger, events):
lastevent = max([e[0] for e in events]) lastevent = max([e[0] for e in events])
counter = Signal(bits_for(lastevent)) counter = Signal(max=lastevent+1)
counterlogic = If(counter != 0, counterlogic = If(counter != 0,
counter.eq(counter + 1) counter.eq(counter + 1)

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@ -5,8 +5,7 @@ from migen.fhdl.structure import *
class RoundRobin: class RoundRobin:
def __init__(self, n, switch_policy=SP_WITHDRAW): def __init__(self, n, switch_policy=SP_WITHDRAW):
self.n = n self.n = n
self.bn = bits_for(self.n-1) self.request = Signal(max=self.n)
self.request = Signal(self.n)
self.grant = Signal(self.bn) self.grant = Signal(self.bn)
self.switch_policy = switch_policy self.switch_policy = switch_policy
if self.switch_policy == SP_CE: if self.switch_policy == SP_CE:

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@ -112,7 +112,7 @@ class SequentialActor(BinaryActor):
def get_binary_control_fragment(self, stb_i, ack_o, stb_o, ack_i): def get_binary_control_fragment(self, stb_i, ack_o, stb_o, ack_i):
ready = Signal() ready = Signal()
timer = Signal(bits_for(self.delay)) timer = Signal(max=self.delay+1)
comb = [ready.eq(timer == 0)] comb = [ready.eq(timer == 0)]
sync = [ sync = [
If(self.trigger, If(self.trigger,