mirror of
https://github.com/enjoy-digital/litex.git
synced 2025-01-04 09:52:26 -05:00
cva6: Improving JTAG debug support
Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat
parent
6a73e4c5fb
commit
d90f8809b4
2 changed files with 63 additions and 91 deletions
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@ -184,24 +184,20 @@ class CVA6(CPU):
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add_manifest_sources(platform, os.path.join(wrapper_root, "Flist.cva6_wrapper"))
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def add_jtag(self, pads):
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from migen.fhdl.specials import Tristate
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self.jtag_tck = Signal()
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self.jtag_tms = Signal()
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self.jtag_trst = Signal()
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self.jtag_tdi = Signal()
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self.jtag_tdo = Signal()
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tdo_o = Signal()
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tdo_oe = Signal()
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self.specials += Tristate(self.jtag_tdo, tdo_o, tdo_oe)
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self.cpu_params.update(
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i_trst_n = self.jtag_trst,
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i_tck = self.jtag_tck,
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i_tms = self.jtag_tms,
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i_tdi = self.jtag_tdi,
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o_tdo = tdo_o,
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o_tdo_oe = tdo_oe,
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o_tdo = self.jtag_tdo,
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)
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def set_reset_address(self, reset_address):
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@ -210,4 +206,6 @@ class CVA6(CPU):
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def do_finalize(self):
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assert hasattr(self, "reset_address")
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if "i_trst_n" not in self.cpu_params:
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self.cpu_params["i_trst_n"] = 1
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self.specials += Instance("cva6_wrapper", **self.cpu_params)
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@ -139,7 +139,8 @@ logic dmactive;
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logic [1:0] irq;
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assign test_en = 1'b0;
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assign ndmreset_n = ~ndmreset;
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always @(posedge clk_i)
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ndmreset_n <= ~ndmreset || rst_n;
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// ---------------
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// AXI Xbar
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@ -166,7 +167,7 @@ localparam axi_pkg::xbar_cfg_t AXI_XBAR_CFG = '{
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UniqueIds: 1'b0,
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AxiAddrWidth: AxiAddrWidth,
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AxiDataWidth: AxiDataWidth,
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NoAddrRules: NBSlave
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NoAddrRules: NBMaster
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};
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axi_xbar_intf #(
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@ -281,103 +282,76 @@ axi2mem #(
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if (riscv::XLEN==32 ) begin
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axi_slave_req_t axi_dmi_slv_req;
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axi_slave_resp_t axi_dmi_slv_resp;
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axi_dm_slave_req_t axi_dmi_mst_req;
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axi_dm_slave_resp_t axi_dmi_mst_resp;
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`AXI_ASSIGN_TO_REQ(axi_dmi_slv_req, master[cva6_wrapper_pkg::Debug])
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`AXI_ASSIGN_FROM_RESP(master[cva6_wrapper_pkg::Debug], axi_dmi_slv_resp)
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`AXI_ASSIGN_FROM_REQ(master_to_dm[0], axi_dmi_mst_req)
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`AXI_ASSIGN_TO_RESP(axi_dmi_mst_resp, master_to_dm[0])
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assign master[cva6_wrapper_pkg::Debug].r_user ='0;
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assign master[cva6_wrapper_pkg::Debug].b_user ='0;
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axi_dw_converter #(
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.AxiMaxReads(1),
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.AxiSlvPortDataWidth(64),
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.AxiMstPortDataWidth(32),
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.AxiAddrWidth(AxiAddrWidth),
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.AxiIdWidth(5),
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.aw_chan_t(ariane_axi::aw_chan_t),
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.slv_w_chan_t(axi_slave_w_chan_t),
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.mst_w_chan_t(axi_dm_slave_w_chan_t),
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.b_chan_t(axi_slave_b_chan_t),
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.ar_chan_t(axi_slave_ar_chan_t),
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.mst_r_chan_t(axi_dm_slave_r_chan_t),
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.slv_r_chan_t(axi_slave_r_chan_t),
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.axi_slv_req_t(axi_slave_req_t),
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.axi_slv_resp_t(axi_slave_resp_t),
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.axi_mst_req_t(axi_dm_slave_req_t),
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.axi_mst_resp_t(axi_dm_slave_resp_t)
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) i_downsizer_dm_slave (
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.clk_i(clk_i),
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axi_dw_converter_intf #(
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.AXI_MAX_READS (1 ),
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.AXI_ADDR_WIDTH (64 ),
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.AXI_ID_WIDTH (AxiIdWidthSlaves ),
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.AXI_SLV_PORT_DATA_WIDTH(64 ),
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.AXI_MST_PORT_DATA_WIDTH(32 ),
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.AXI_USER_WIDTH (AxiUserWidth )
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) i_dw_converter (
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.clk_i (clk_i),
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.rst_ni(ndmreset_n),
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.slv_req_i(axi_dmi_slv_req),
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.slv_resp_o(axi_dmi_slv_resp),
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.mst_req_o(axi_dmi_mst_req),
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.mst_resp_i(axi_dmi_mst_resp)
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.slv (master[cva6_wrapper_pkg::Debug]),
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.mst (master_to_dm[0])
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);
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end else begin
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assign master[cva6_wrapper_pkg::Debug].aw_id = master_to_dm[0].aw_id;
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assign master[cva6_wrapper_pkg::Debug].aw_addr = master_to_dm[0].aw_addr;
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assign master[cva6_wrapper_pkg::Debug].aw_len = master_to_dm[0].aw_len;
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assign master[cva6_wrapper_pkg::Debug].aw_size = master_to_dm[0].aw_size;
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assign master[cva6_wrapper_pkg::Debug].aw_burst = master_to_dm[0].aw_burst;
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assign master[cva6_wrapper_pkg::Debug].aw_lock = master_to_dm[0].aw_lock;
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assign master[cva6_wrapper_pkg::Debug].aw_cache = master_to_dm[0].aw_cache;
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assign master[cva6_wrapper_pkg::Debug].aw_prot = master_to_dm[0].aw_prot;
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assign master[cva6_wrapper_pkg::Debug].aw_qos = master_to_dm[0].aw_qos;
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assign master[cva6_wrapper_pkg::Debug].aw_atop = master_to_dm[0].aw_atop;
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assign master[cva6_wrapper_pkg::Debug].aw_region = master_to_dm[0].aw_region;
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assign master[cva6_wrapper_pkg::Debug].aw_user = master_to_dm[0].aw_user;
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assign master[cva6_wrapper_pkg::Debug].aw_valid = master_to_dm[0].aw_valid;
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assign master_to_dm[0].aw_id = master[cva6_wrapper_pkg::Debug].aw_id;
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assign master_to_dm[0].aw_addr = master[cva6_wrapper_pkg::Debug].aw_addr;
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assign master_to_dm[0].aw_len = master[cva6_wrapper_pkg::Debug].aw_len;
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assign master_to_dm[0].aw_size = master[cva6_wrapper_pkg::Debug].aw_size;
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assign master_to_dm[0].aw_burst = master[cva6_wrapper_pkg::Debug].aw_burst;
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assign master_to_dm[0].aw_lock = master[cva6_wrapper_pkg::Debug].aw_lock;
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assign master_to_dm[0].aw_cache = master[cva6_wrapper_pkg::Debug].aw_cache;
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assign master_to_dm[0].aw_prot = master[cva6_wrapper_pkg::Debug].aw_prot;
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assign master_to_dm[0].aw_qos = master[cva6_wrapper_pkg::Debug].aw_qos;
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assign master_to_dm[0].aw_atop = master[cva6_wrapper_pkg::Debug].aw_atop;
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assign master_to_dm[0].aw_region = master[cva6_wrapper_pkg::Debug].aw_region;
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assign master_to_dm[0].aw_user = master[cva6_wrapper_pkg::Debug].aw_user;
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assign master_to_dm[0].aw_valid = master[cva6_wrapper_pkg::Debug].aw_valid;
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assign master_to_dm[0].aw_ready =master[cva6_wrapper_pkg::Debug].aw_ready;
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assign master[cva6_wrapper_pkg::Debug].aw_ready = master_to_dm[0].aw_ready;
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assign master[cva6_wrapper_pkg::Debug].w_data = master_to_dm[0].w_data;
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assign master[cva6_wrapper_pkg::Debug].w_strb = master_to_dm[0].w_strb;
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assign master[cva6_wrapper_pkg::Debug].w_last = master_to_dm[0].w_last;
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assign master[cva6_wrapper_pkg::Debug].w_user = master_to_dm[0].w_user;
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assign master[cva6_wrapper_pkg::Debug].w_valid = master_to_dm[0].w_valid;
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assign master_to_dm[0].w_data = master[cva6_wrapper_pkg::Debug].w_data;
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assign master_to_dm[0].w_strb = master[cva6_wrapper_pkg::Debug].w_strb;
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assign master_to_dm[0].w_last = master[cva6_wrapper_pkg::Debug].w_last;
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assign master_to_dm[0].w_user = master[cva6_wrapper_pkg::Debug].w_user;
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assign master_to_dm[0].w_valid = master[cva6_wrapper_pkg::Debug].w_valid;
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assign master_to_dm[0].w_ready =master[cva6_wrapper_pkg::Debug].w_ready;
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assign master[cva6_wrapper_pkg::Debug].w_ready = master_to_dm[0].w_ready;
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assign master_to_dm[0].b_id =master[cva6_wrapper_pkg::Debug].b_id;
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assign master_to_dm[0].b_resp =master[cva6_wrapper_pkg::Debug].b_resp;
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assign master_to_dm[0].b_user =master[cva6_wrapper_pkg::Debug].b_user;
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assign master_to_dm[0].b_valid =master[cva6_wrapper_pkg::Debug].b_valid;
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assign master[cva6_wrapper_pkg::Debug].b_id = master_to_dm[0].b_id;
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assign master[cva6_wrapper_pkg::Debug].b_resp = master_to_dm[0].b_resp;
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assign master[cva6_wrapper_pkg::Debug].b_user = master_to_dm[0].b_user;
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assign master[cva6_wrapper_pkg::Debug].b_valid = master_to_dm[0].b_valid;
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assign master[cva6_wrapper_pkg::Debug].b_ready = master_to_dm[0].b_ready;
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assign master_to_dm[0].b_ready = master[cva6_wrapper_pkg::Debug].b_ready;
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assign master[cva6_wrapper_pkg::Debug].ar_id = master_to_dm[0].ar_id;
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assign master[cva6_wrapper_pkg::Debug].ar_addr = master_to_dm[0].ar_addr;
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assign master[cva6_wrapper_pkg::Debug].ar_len = master_to_dm[0].ar_len;
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assign master[cva6_wrapper_pkg::Debug].ar_size = master_to_dm[0].ar_size;
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assign master[cva6_wrapper_pkg::Debug].ar_burst = master_to_dm[0].ar_burst;
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assign master[cva6_wrapper_pkg::Debug].ar_lock = master_to_dm[0].ar_lock;
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assign master[cva6_wrapper_pkg::Debug].ar_cache = master_to_dm[0].ar_cache;
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assign master[cva6_wrapper_pkg::Debug].ar_prot = master_to_dm[0].ar_prot;
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assign master[cva6_wrapper_pkg::Debug].ar_qos = master_to_dm[0].ar_qos;
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assign master[cva6_wrapper_pkg::Debug].ar_region = master_to_dm[0].ar_region;
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assign master[cva6_wrapper_pkg::Debug].ar_user = master_to_dm[0].ar_user;
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assign master[cva6_wrapper_pkg::Debug].ar_valid = master_to_dm[0].ar_valid;
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assign master_to_dm[0].ar_id = master[cva6_wrapper_pkg::Debug].ar_id;
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assign master_to_dm[0].ar_addr = master[cva6_wrapper_pkg::Debug].ar_addr;
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assign master_to_dm[0].ar_len = master[cva6_wrapper_pkg::Debug].ar_len;
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assign master_to_dm[0].ar_size = master[cva6_wrapper_pkg::Debug].ar_size;
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assign master_to_dm[0].ar_burst = master[cva6_wrapper_pkg::Debug].ar_burst;
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assign master_to_dm[0].ar_lock = master[cva6_wrapper_pkg::Debug].ar_lock;
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assign master_to_dm[0].ar_cache = master[cva6_wrapper_pkg::Debug].ar_cache;
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assign master_to_dm[0].ar_prot = master[cva6_wrapper_pkg::Debug].ar_prot;
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assign master_to_dm[0].ar_qos = master[cva6_wrapper_pkg::Debug].ar_qos;
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assign master_to_dm[0].ar_region = master[cva6_wrapper_pkg::Debug].ar_region;
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assign master_to_dm[0].ar_user = master[cva6_wrapper_pkg::Debug].ar_user;
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assign master_to_dm[0].ar_valid = master[cva6_wrapper_pkg::Debug].ar_valid;
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assign master_to_dm[0].ar_ready =master[cva6_wrapper_pkg::Debug].ar_ready;
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assign master[cva6_wrapper_pkg::Debug].ar_ready = master_to_dm[0].ar_ready;
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assign master_to_dm[0].r_id =master[cva6_wrapper_pkg::Debug].r_id;
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assign master_to_dm[0].r_data =master[cva6_wrapper_pkg::Debug].r_data;
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assign master_to_dm[0].r_resp =master[cva6_wrapper_pkg::Debug].r_resp;
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assign master_to_dm[0].r_last =master[cva6_wrapper_pkg::Debug].r_last;
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assign master_to_dm[0].r_user =master[cva6_wrapper_pkg::Debug].r_user;
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assign master_to_dm[0].r_valid =master[cva6_wrapper_pkg::Debug].r_valid;
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assign master[cva6_wrapper_pkg::Debug].r_id = master_to_dm[0].r_id;
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assign master[cva6_wrapper_pkg::Debug].r_data = master_to_dm[0].r_data;
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assign master[cva6_wrapper_pkg::Debug].r_resp = master_to_dm[0].r_resp;
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assign master[cva6_wrapper_pkg::Debug].r_last = master_to_dm[0].r_last;
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assign master[cva6_wrapper_pkg::Debug].r_user = master_to_dm[0].r_user;
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assign master[cva6_wrapper_pkg::Debug].r_valid = master_to_dm[0].r_valid;
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assign master[cva6_wrapper_pkg::Debug].r_ready = master_to_dm[0].r_ready;
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assign master_to_dm[0].r_ready = master[cva6_wrapper_pkg::Debug].r_ready;
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end
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@ -427,7 +401,7 @@ ariane #(
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.ArianeCfg ( cva6_wrapper_pkg::CVA6Cfg )
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) i_ariane (
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.clk_i ( clk_i ),
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.rst_ni ( rst_n /*ndmreset_n*/ ),
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.rst_ni ( ndmreset_n ),
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.boot_addr_i ( cva6_wrapper_pkg::ExternalBase ),
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.hart_id_i ( '0 ),
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.irq_i ( irq ),
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