gen/fhdl/verilog: fix signed init values

2020-01-12 22:06:35 +01:00 · 2020-01-12 22:06:35 +01:00 · d92bd8ffaa
parent ff066a5e09
commit d92bd8ffaa
1 changed files with 2 additions and 2 deletions
--- a/litex/gen/fhdl/verilog.py
+++ b/litex/gen/fhdl/verilog.py
@ -59,8 +59,8 @@ def _printsig(ns, s):

 def _printconstant(node):
    if node.signed:
-        return (str(node.nbits) + "'sd" + str(2**node.nbits + node.value),
-                True)
+        sign = "-" if node.value < 0 else ""
+        return (sign + str(node.nbits) + "'d" + str(abs(node.value)), True)
    else:
        return str(node.nbits) + "'d" + str(node.value), False