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gen/fhdl/verilog: fix signed init values

This commit is contained in:
Florent Kermarrec 2020-01-12 22:06:35 +01:00
parent ff066a5e09
commit d92bd8ffaa
1 changed files with 2 additions and 2 deletions
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4
litex/gen/fhdl/verilog.py
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@ -59,8 +59,8 @@ def _printsig(ns, s):
def _printconstant(node): def _printconstant(node):
if node.signed: if node.signed:
return (str(node.nbits) + "'sd" + str(2**node.nbits + node.value), sign = "-" if node.value < 0 else ""
True) return (sign + str(node.nbits) + "'d" + str(abs(node.value)), True)
else: else:
return str(node.nbits) + "'d" + str(node.value), False return str(node.nbits) + "'d" + str(node.value), False