build/efinix/ifacewriter, soc/cores/ram/efinix_hyperram: adding F100 internal HyperRAM support
This commit is contained in:
Gwenhael Goavec-Merou
parent
6f02a7f508
commit
d95d5bdce9
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@ -447,6 +447,41 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True)
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return '\n'.join(cmd)
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def generate_hyperram(self, block, verbose=True):
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block_type = "HYPERRAM"
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pads = block["pads"]
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name = block["name"]
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location = block["location"]
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ctl_clk = block["ctl_clk"].name_override
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cal_clk = block["cal_clk"].name_override
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clk90_clk = block["clk90_clk"].name_override
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cmd = []
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cmd.append('design.create_block("{}", "{}")'.format(name, block_type))
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cmd.append('design.set_property("{}", "CK_N_HI_PIN", "{}", "{}")'.format(name, pads.clkn_h.name, block_type))
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cmd.append('design.set_property("{}", "CK_N_LO_PIN", "{}", "{}")'.format(name, pads.clkn_l.name, block_type))
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cmd.append('design.set_property("{}", "CK_P_HI_PIN", "{}", "{}")'.format(name, pads.clkp_h.name, block_type))
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cmd.append('design.set_property("{}", "CK_P_LO_PIN", "{}", "{}")'.format(name, pads.clkp_l.name, block_type))
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cmd.append('design.set_property("{}", "CLK90_PIN", "{}", "{}")'.format(name, clk90_clk, block_type))
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cmd.append('design.set_property("{}", "CLKCAL_PIN", "{}", "{}")'.format(name, cal_clk, block_type))
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cmd.append('design.set_property("{}", "CLK_PIN", "{}", "{}")'.format(name, ctl_clk, block_type))
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cmd.append('design.set_property("{}", "CS_N_PIN", "{}", "{}")'.format(name, pads.csn.name, block_type))
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cmd.append('design.set_property("{}", "DQ_IN_HI_PIN", "{}", "{}")'.format(name, pads.dq_i_h.name, block_type))
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cmd.append('design.set_property("{}", "DQ_IN_LO_PIN", "{}", "{}")'.format(name, pads.dq_i_l.name, block_type))
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cmd.append('design.set_property("{}", "DQ_OE_PIN", "{}", "{}")'.format(name, pads.dq_oe.name, block_type))
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cmd.append('design.set_property("{}", "DQ_OUT_HI_PIN", "{}", "{}")'.format(name, pads.dq_o_h.name, block_type))
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cmd.append('design.set_property("{}", "DQ_OUT_LO_PIN", "{}", "{}")'.format(name, pads.dq_o_l.name, block_type))
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cmd.append('design.set_property("{}", "RST_N_PIN", "{}", "{}")'.format(name, pads.rstn.name, block_type))
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cmd.append('design.set_property("{}", "RWDS_IN_HI_PIN", "{}", "{}")'.format(name, pads.rwds_i_h.name, block_type))
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cmd.append('design.set_property("{}", "RWDS_IN_LO_PIN", "{}", "{}")'.format(name, pads.rwds_i_l.name, block_type))
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cmd.append('design.set_property("{}", "RWDS_OE_PIN", "{}", "{}")'.format(name, pads.rwds_oe.name, block_type))
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cmd.append('design.set_property("{}", "RWDS_OUT_HI_PIN", "{}", "{}")'.format(name, pads.rwds_o_h.name, block_type))
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cmd.append('design.set_property("{}", "RWDS_OUT_LO_PIN", "{}", "{}")'.format(name, pads.rwds_o_l.name, block_type))
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cmd.append('design.assign_resource("{}", "{}", "{}")\n'.format(name, location, block_type))
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return '\n'.join(cmd) + '\n'
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def generate(self, partnumber):
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output = ""
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for block in self.blocks:
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@ -463,6 +498,8 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True)
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output += self.generate_mipi_rx(block)
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if block["type"] == "LVDS":
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output += self.generate_lvds(block)
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if block["type"] == "HYPERRAM":
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output += self.generate_hyperram(block)
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if block["type"] == "JTAG":
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output += self.generate_jtag(block)
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return output
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@ -0,0 +1,138 @@
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#
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# This file is part of LiteHyperBus
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#
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# Copyright (c) 2023 Gwenhael Goavec-Merou <gwenhael@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.build.generic_platform import *
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from litex.gen import *
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from litex.gen.genlib.misc import WaitTimer
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from litex.build.io import DifferentialOutput
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.clock.efinix import TITANIUMPLL
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from litex.soc.cores.hyperbus import HyperRAM
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# HyperRAM (efinix F100) ---------------------------------------------------------------------------
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class EfinixHyperRAM(HyperRAM):
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""" HyperRAM wrapper for efinix F100 (internal)
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"""
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def __init__(self, platform, latency=6, clock_domain="sys", sys_clk_freq=None):
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# # #
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assert sys_clk_freq is not None and sys_clk_freq * 2 < 250e6
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_io = [
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("hyperram", 0,
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Subsignal("clkp_h", 0, Pins(1)),
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Subsignal("clkp_l", 0, Pins(1)),
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Subsignal("clkn_h", 0, Pins(1)),
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Subsignal("clkn_l", 0, Pins(1)),
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Subsignal("dq_o_h", 0, Pins(16)),
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Subsignal("dq_o_l", 0, Pins(16)),
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Subsignal("dq_i_h", 0, Pins(16)),
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Subsignal("dq_i_l", 0, Pins(16)),
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Subsignal("dq_oe", 0, Pins(16)),
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Subsignal("rwds_o_h", 0, Pins(2)),
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Subsignal("rwds_o_l", 0, Pins(2)),
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Subsignal("rwds_i_h", 0, Pins(2)),
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Subsignal("rwds_i_l", 0, Pins(2)),
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Subsignal("rwds_oe", 0, Pins(2)),
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Subsignal("csn", 0, Pins(1)),
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Subsignal("rstn", 0, Pins(1)),
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)]
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# PLL dyn phase shift
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platform.add_extension([
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("shift_ena", 0, Pins(1)),
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("shift_sel", 0, Pins(1)),
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("shift", 0, Pins(1)),
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])
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_dps_pads = {
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"shift_ena" : platform.request("shift_ena"),
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"shift_sel" : platform.request("shift_sel"),
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"shift" : platform.request("shift"),
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}
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platform.toolchain.excluded_ios.append(_dps_pads["shift_ena"])
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platform.toolchain.excluded_ios.append(_dps_pads["shift_sel"])
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platform.toolchain.excluded_ios.append(_dps_pads["shift"])
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# PLL.
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self.pll = pll = TITANIUMPLL(platform, dyn_phase_shift_pads=_dps_pads)
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pll.register_clkin(ClockDomain(clock_domain).clk, sys_clk_freq, clock_domain)
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pll.create_clkout(None, sys_clk_freq)
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pll.create_clkout(None, sys_clk_freq*2, name="hp_clk", with_reset=True)
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pll.create_clkout(None, sys_clk_freq*2, phase=90, name="hp90_clk", with_reset=True)
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pll.create_clkout(None, sys_clk_freq*2, name="hpcal_clk", with_reset=True, dyn_phase=True)
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# connect HyperRAM to interface designer block
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class HPPads:
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def __init__(self):
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self.dq = TSTriple(16)
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self.rwds = TSTriple(2)
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self.cs_n = Signal(1)
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self.rst_n = Signal(1)
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self.clk = Signal(1)
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_hp_pads = HPPads()
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platform.add_extension(_io)
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self.io_pads = _io_pads = platform.request("hyperram")
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self.comb += [
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_io_pads.clkp_l.eq(_hp_pads.clk),
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_io_pads.clkp_h.eq(_hp_pads.clk),
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_io_pads.clkn_l.eq(~_hp_pads.clk),
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_io_pads.clkn_h.eq(~_hp_pads.clk),
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_io_pads.dq_o_h.eq(_hp_pads.dq.o),
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_io_pads.dq_o_l.eq(_hp_pads.dq.o),
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_hp_pads.dq.i.eq(_io_pads.dq_i_h | _io_pads.dq_i_l),
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_io_pads.dq_oe.eq(Replicate(_hp_pads.dq.oe[0], 16)),
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_io_pads.rwds_o_h.eq(_hp_pads.rwds.o),
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_io_pads.rwds_o_l.eq(_hp_pads.rwds.o),
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_hp_pads.rwds.i.eq(_io_pads.rwds_i_h | _io_pads.rwds_i_l),
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_io_pads.rwds_oe.eq(Replicate(_hp_pads.rwds.oe[0], 2)),
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_io_pads.csn.eq(_hp_pads.cs_n),
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_io_pads.rstn.eq(_hp_pads.rst_n),
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]
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block = {
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"type" : "HYPERRAM",
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"name" : "hp_inst",
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"location" : "HYPER_RAM0",
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"pads" : _io_pads,
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"ctl_clk" : ClockDomain("hp").clk,
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"cal_clk" : ClockDomain("hpcal").clk,
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"clk90_clk" : ClockDomain("hp90").clk,
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}
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platform.toolchain.ifacewriter.blocks.append(block)
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platform.toolchain.excluded_ios.append(_io_pads.clkp_h)
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platform.toolchain.excluded_ios.append(_io_pads.clkp_l)
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platform.toolchain.excluded_ios.append(_io_pads.clkn_h)
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platform.toolchain.excluded_ios.append(_io_pads.clkn_l)
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platform.toolchain.excluded_ios.append(_io_pads.dq_o_h)
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platform.toolchain.excluded_ios.append(_io_pads.dq_o_l)
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platform.toolchain.excluded_ios.append(_io_pads.dq_i_h)
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platform.toolchain.excluded_ios.append(_io_pads.dq_i_l)
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platform.toolchain.excluded_ios.append(_io_pads.dq_oe)
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platform.toolchain.excluded_ios.append(_io_pads.rwds_o_h)
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platform.toolchain.excluded_ios.append(_io_pads.rwds_o_l)
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platform.toolchain.excluded_ios.append(_io_pads.rwds_i_l)
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platform.toolchain.excluded_ios.append(_io_pads.rwds_i_h)
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platform.toolchain.excluded_ios.append(_io_pads.rwds_oe)
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platform.toolchain.excluded_ios.append(_io_pads.csn)
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platform.toolchain.excluded_ios.append(_io_pads.rstn)
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HyperRAM.__init__(self, _hp_pads, latency, sys_clk_freq)
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