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targets/core: generate status/BIST ios

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This commit is contained in:
Florent Kermarrec 2015-01-25 11:23:39 +01:00
parent 9960ca010a
commit d97ec9235b
1 changed files with 20 additions and 1 deletions
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21
targets/core.py
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@ -11,7 +11,7 @@ class LiteSATACore(Module):
# SATA PHY/Core/Frontend # SATA PHY/Core/Frontend
self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata"), "sata_gen2", clk_freq) self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata"), "sata_gen2", clk_freq)
self.submodules.sata = LiteSATA(self.sata_phy) self.submodules.sata = LiteSATA(self.sata_phy, with_bist=True)
# Get user ports from crossbar # Get user ports from crossbar
self.user_ports = self.sata.crossbar.get_ports(nports) self.user_ports = self.sata.crossbar.get_ports(nports)
@ -25,6 +25,25 @@ class LiteSATACore(Module):
if isinstance(obj, Signal): if isinstance(obj, Signal):
ios = ios.union({obj}) ios = ios.union({obj})
# Status
ios = ios.union({
self.sata_phy.crg.ready,
self.sata_phy.ctrl.ready
})
# BIST
if hasattr(self.sata, "bist"):
for bist_unit in ["generator", "checker"]:
for signal in ["start", "sector", "count", "random", "done", "aborted", "errors"]:
ios = ios.union({getattr(getattr(self.sata.bist, bist_unit), signal)})
ios = ios.union({
self.sata.bist.identify.start,
self.sata.bist.identify.done,
self.sata.bist.identify.source.stb,
self.sata.bist.identify.source.data,
self.sata.bist.identify.source.ack
})
# User ports # User ports
def _iter_layout(layout): def _iter_layout(layout):
for e in layout: for e in layout: