README: Core Logic, Bus, Bank
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README
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README
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@ -78,8 +78,8 @@ cluttered syntax at times when writing descriptions in FHDL, but we
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believe this is totally acceptable, particularly when compared to VHDL
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believe this is totally acceptable, particularly when compared to VHDL
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;-)
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;-)
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Migen is made up of several related components, which are described
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Migen is made up of several related components, which are briefly
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below.
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described below.
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Migen FHDL
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Migen FHDL
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==========
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==========
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@ -237,16 +237,16 @@ For convenience, there is also a Elif() method.
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Example:
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Example:
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If(tx_count16 == 0,
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If(tx_count16 == 0,
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tx_bitcount.be(tx_bitcount + 1),
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tx_bitcount.be(tx_bitcount + 1),
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If(tx_bitcount == 8,
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If(tx_bitcount == 8,
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self.tx.be(1)
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self.tx.be(1)
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).Elif(tx_bitcount == 9,
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).Elif(tx_bitcount == 9,
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self.tx.be(1),
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self.tx.be(1),
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tx_busy.be(0)
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tx_busy.be(0)
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).Else(
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).Else(
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self.tx.be(tx_reg[0]),
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self.tx.be(tx_reg[0]),
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tx_reg.be(Cat(tx_reg[1:], 0))
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tx_reg.be(Cat(tx_reg[1:], 0))
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)
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)
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)
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)
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Case statement
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Case statement
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@ -317,10 +317,19 @@ autofragment module.
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Migen Core Logic
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Migen Core Logic
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================
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================
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Migen Core Logic is a convenience library of common logic circuits
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implemented using FHDL:
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- a multi-cycle integer divider.
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- a round-robin arbiter, useful to build bus arbiters.
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- a multiplexer bank (multimux), useful to multiplex composite
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(grouped) signals.
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- a condition-triggered static scheduler of FHDL synchronous statements
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(timeline).
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Migen Bus
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Migen Bus
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=========
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=========
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Migen Bus contains classes providing a common structure for master and
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slave interfaces of the following buses:
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- Wishbone [5], the general purpose bus recommended by Opencores.
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- Wishbone [5], the general purpose bus recommended by Opencores.
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- CSR-NG, a low-bandwidth, resource-sensitive bus designed for
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- CSR-NG, a low-bandwidth, resource-sensitive bus designed for
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accessing the configuration and status registers of cores from
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accessing the configuration and status registers of cores from
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@ -328,9 +337,57 @@ Migen Bus
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- FastMemoryLink-NG, a split-transaction bus optimized for use with a
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- FastMemoryLink-NG, a split-transaction bus optimized for use with a
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high-performance, out-of-order SDRAM controller. (TODO)
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high-performance, out-of-order SDRAM controller. (TODO)
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It also provides interconnect components for these buses, such as
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arbiters and address decoders. The strength of the Migen procedurally
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generated logic can be illustrated by the following example:
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wbcon = wishbone.InterconnectShared(
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[cpu.ibus, cpu.dbus, ethernet.dma, audio.dma],
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[(0, norflash.bus), (1, wishbone2fml.wishbone),
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(3, wishbone2csr.wishbone)])
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In this example, the interconnect component generates a 4-way round-robin
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arbiter, multiplexes the master bus signals into a shared bus, determines
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that the address decoding must occur on 2 bits, and connects all slave
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interfaces to the shared bus, inserting the address decoder logic in the
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bus cycle qualification signals and multiplexing the data return path. It
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can recognize the signals in each core's bus interface thanks to the
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common structure mandated by Migen Bus. All this happens automatically,
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using only that much user code. The resulting interconnect logic can be
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retrieved using wbcon.get_fragment(), and combined with the fragments
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from the rest of the system.
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Migen Bank
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Migen Bank
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==========
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==========
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Migen Bank is a system comparable to wishbone-gen [6], which automates
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the creation of configuration and status register banks and
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(TODO) interrupt/event managers implemented in cores.
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Bank takes a description made up of a list of registers and generates
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logic implementing it with a slave interface compatible with Migen Bus.
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A register can be "raw", which means that the core has direct access to
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it. It also means that the register width must be less or equal to the
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bus word width. In that case, the register object provides the following
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signals:
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- dev_r, which contains the data written from the bus interface.
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- dev_re, which is the strobe signal for dev_r. It is active for one
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cycle, after or during a write from the bus. dev_r is only valid when
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dev_re is high.
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- dev_w, which must provide at all times the value to be read from the
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bus.
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Registers that are not raw are managed by Bank and contain fields. If the
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sum of the widths of all fields attached to a register exceeds the bus
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word width, the register will automatically be sliced into words of the
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maximum size and implemented at consecutive bus addresses, MSB first.
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Field objects have two parameters, access_bus and access_dev, determining
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respectively the access policies for the bus and core sides. They can
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take the values READ_ONLY, WRITE_ONLY and READ_WRITE.
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If the device can read, the field object provides the dev_r signal, which
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contains at all times the current value of the field (kept by the logic
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generated by Bank).
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If the device can write, the field object provides the following signals:
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- dev_w, which provides the value to be written into the field.
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- dev_we, which strobes the value into the field.
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Migen Flow
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Migen Flow
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==========
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==========
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@ -344,6 +401,7 @@ References:
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[3] http://milkymist.org/thesis/thesis.pdf
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[3] http://milkymist.org/thesis/thesis.pdf
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[4] http://www.xilinx.com/publications/archives/xcell/Xcell77.pdf p30-35
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[4] http://www.xilinx.com/publications/archives/xcell/Xcell77.pdf p30-35
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[5] http://cdn.opencores.org/downloads/wbspec_b4.pdf
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[5] http://cdn.opencores.org/downloads/wbspec_b4.pdf
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[6] http://www.ohwr.org/projects/wishbone-gen
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Practical information
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Practical information
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=====================
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=====================
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