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cif: fix indentation
This commit is contained in:
Sebastien Bourdeauducq
parent
fb06d803e1
commit
da2b7aa961
1 changed files with 115 additions and 115 deletions
228
milkymist/cif.py
228
milkymist/cif.py
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@ -67,30 +67,30 @@ def get_csr_header(csr_base, bank_array, interrupt_map):
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return r
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return r
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def get_sdram_phy_header(sdram_phy):
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def get_sdram_phy_header(sdram_phy):
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if sdram_phy.phy_settings.type not in ["SDR", "DDR", "LPDDR", "DDR2"]:
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if sdram_phy.phy_settings.type not in ["SDR", "DDR", "LPDDR", "DDR2"]:
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raise NotImplementedError("The SDRAM PHY header generator only supports SDR, DDR, LPDDR and DDR2")
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raise NotImplementedError("The SDRAM PHY header generator only supports SDR, DDR, LPDDR and DDR2")
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r = "#ifndef __HW_SDRAM_PHY_H\n#define __HW_SDRAM_PHY_H\n"
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r = "#ifndef __HW_SDRAM_PHY_H\n#define __HW_SDRAM_PHY_H\n"
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r += "#include <hw/common.h>\n#include <hw/csr.h>\n#include <hw/flags.h>\n\n"
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r += "#include <hw/common.h>\n#include <hw/csr.h>\n#include <hw/flags.h>\n\n"
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r += "static void cdelay(int i);\n"
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r += "static void cdelay(int i);\n"
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#
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#
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# commands_px functions
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# commands_px functions
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#
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#
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for n in range(sdram_phy.phy_settings.nphases):
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for n in range(sdram_phy.phy_settings.nphases):
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r += """
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r += """
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static void command_p{n}(int cmd)
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static void command_p{n}(int cmd)
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{{
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{{
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dfii_pi{n}_command_write(cmd);
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dfii_pi{n}_command_write(cmd);
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dfii_pi{n}_command_issue_write(1);
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dfii_pi{n}_command_issue_write(1);
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}}""".format(n=str(n))
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}}""".format(n=str(n))
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r += "\n\n"
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r += "\n\n"
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#
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#
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# rd/wr access macros
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# rd/wr access macros
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#
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#
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r += """
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r += """
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#define dfii_pird_address_write(X) dfii_pi{rdphase}_address_write(X)
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#define dfii_pird_address_write(X) dfii_pi{rdphase}_address_write(X)
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#define dfii_piwr_address_write(X) dfii_pi{wrphase}_address_write(X)
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#define dfii_piwr_address_write(X) dfii_pi{wrphase}_address_write(X)
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@ -100,105 +100,105 @@ static void command_p{n}(int cmd)
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#define command_prd(X) command_p{rdphase}(X)
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#define command_prd(X) command_p{rdphase}(X)
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#define command_pwr(X) command_p{wrphase}(X)
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#define command_pwr(X) command_p{wrphase}(X)
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""".format(rdphase=str(sdram_phy.phy_settings.rdphase), wrphase=str(sdram_phy.phy_settings.wrphase))
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""".format(rdphase=str(sdram_phy.phy_settings.rdphase), wrphase=str(sdram_phy.phy_settings.wrphase))
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r +="\n"
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r +="\n"
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#
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#
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# init sequence
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# init sequence
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#
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#
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cmds = {
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cmds = {
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"PRECHARGE_ALL" : "DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
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"PRECHARGE_ALL" : "DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
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"MODE_REGISTER" : "DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
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"MODE_REGISTER" : "DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
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"AUTO_REFRESH" : "DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS",
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"AUTO_REFRESH" : "DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS",
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"CKE" : "DFII_CONTROL_CKE"
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"CKE" : "DFII_CONTROL_CKE"
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}
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}
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def gen_cmd(comment, a, ba, cmd, delay):
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r = "\t/* {0} */\n".format(comment)
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r += "\tdfii_pi0_address_write({0:#x});\n".format(a)
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r += "\tdfii_pi0_baddress_write({0:d});\n".format(ba)
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if "CKE" in cmd:
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r += "\tdfii_control_write({0});\n".format(cmd)
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else:
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r += "\tcommand_p0({0});\n".format(cmd)
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r += "\tcdelay({0:d});\n".format(delay)
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r += "\n"
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return r
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r += "static void init_sequence(void)\n{\n"
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cl = sdram_phy.phy_settings.cl
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if sdram_phy.phy_settings.type == "SDR":
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bl = 1*sdram_phy.phy_settings.nphases
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mr = log2_int(bl) + (cl << 4)
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reset_dll = 1 << 8
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init_sequence = [
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("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
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]
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elif sdram_phy.phy_settings.type == "DDR":
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bl = 2*sdram_phy.phy_settings.nphases
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mr = log2_int(bl) + (cl << 4)
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emr = 0
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reset_dll = 1 << 8
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init_sequence = [
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("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Load Extended Mode Register", emr, 1, cmds["MODE_REGISTER"], 0),
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("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
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]
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elif sdram_phy.phy_settings.type == "LPDDR":
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bl = 2*sdram_phy.phy_settings.nphases
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mr = log2_int(bl) + (cl << 4)
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emr = 0
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reset_dll = 1 << 8
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init_sequence = [
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("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Load Extended Mode Register", emr, 2, cmds["MODE_REGISTER"], 0),
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("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
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]
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elif sdram_phy.phy_settings.type == "DDR2":
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bl = 2*sdram_phy.phy_settings.nphases
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mr = log2_int(bl) + (cl << 4)
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emr = 0
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reset_dll = 1 << 8
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init_sequence = [
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("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Load Extended Mode Register", emr, 1, cmds["MODE_REGISTER"], 0),
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("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
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]
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for comment, a, ba, cmd, delay in init_sequence:
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r += gen_cmd(comment, a, ba, cmd, delay)
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r += "}\n"
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r += "#endif\n"
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def gen_cmd(comment, a, ba, cmd, delay):
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r = "\t/* {0} */\n".format(comment)
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r += "\tdfii_pi0_address_write({0:#x});\n".format(a)
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r += "\tdfii_pi0_baddress_write({0:d});\n".format(ba)
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if "CKE" in cmd:
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r += "\tdfii_control_write({0});\n".format(cmd)
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else:
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r += "\tcommand_p0({0});\n".format(cmd)
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r += "\tcdelay({0:d});\n".format(delay)
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r += "\n"
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return r
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return r
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r += "static void init_sequence(void)\n{\n"
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cl = sdram_phy.phy_settings.cl
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if sdram_phy.phy_settings.type == "SDR":
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bl = 1*sdram_phy.phy_settings.nphases
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mr = log2_int(bl) + (cl << 4)
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reset_dll = 1 << 8
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init_sequence = [
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("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
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]
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elif sdram_phy.phy_settings.type == "DDR":
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bl = 2*sdram_phy.phy_settings.nphases
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mr = log2_int(bl) + (cl << 4)
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emr = 0
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reset_dll = 1 << 8
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init_sequence = [
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("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Load Extended Mode Register", emr, 1, cmds["MODE_REGISTER"], 0),
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("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
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]
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elif sdram_phy.phy_settings.type == "LPDDR":
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bl = 2*sdram_phy.phy_settings.nphases
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mr = log2_int(bl) + (cl << 4)
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emr = 0
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reset_dll = 1 << 8
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init_sequence = [
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("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Load Extended Mode Register", emr, 2, cmds["MODE_REGISTER"], 0),
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("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
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]
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elif sdram_phy.phy_settings.type == "DDR2":
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bl = 2*sdram_phy.phy_settings.nphases
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mr = log2_int(bl) + (cl << 4)
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emr = 0
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reset_dll = 1 << 8
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init_sequence = [
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("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Load Extended Mode Register", emr, 1, cmds["MODE_REGISTER"], 0),
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("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
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]
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for comment, a, ba, cmd, delay in init_sequence:
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r += gen_cmd(comment, a, ba, cmd, delay)
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r += "}\n"
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r += "#endif\n"
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return r
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