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rename milkymist-ng to MiSoC

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Sebastien Bourdeauducq 2013-11-09 18:51:16 +01:00
parent 416c8af1e2
commit dad389eef7
2 changed files with 4 additions and 6 deletions
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6
README
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@ -25,14 +25,12 @@ more traditional high-level synthesizer that compiles Python routines into
state machines with datapaths, and a simulator that allows test benches to be state machines with datapaths, and a simulator that allows test benches to be
written in Python. written in Python.
Migen is the foundation of the next-generation Milkymist SoC.
See the doc/ folder for more technical information. See the doc/ folder for more technical information.
Code repository: Code repository:
https://github.com/milkymist/migen https://github.com/milkymist/migen
New Milkymist SoC based on Migen: System-on-chip design based on Migen:
https://github.com/milkymist/milkymist-ng https://github.com/milkymist/misoc
Migen is designed for Python 3.3. Migen is designed for Python 3.3.

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doc/bus.rst
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@ -107,11 +107,11 @@ The first two techniques are explained with more details in [drreorder]_.
.. [drreorder] http://www.xilinx.com/txpatches/pub/documentation/misc/improving%20ddr%20sdram%20efficiency.pdf .. [drreorder] http://www.xilinx.com/txpatches/pub/documentation/misc/improving%20ddr%20sdram%20efficiency.pdf
Migen and milkymist-ng implement their own bus, called LASMIbus, that features the last two techniques. Grouping by row had been previously explored with ASMI, but difficulties in achieving timing closure at reasonable latencies in FPGA combined with uncertain performance pay-off for some applications discouraged work in that direction. Migen and MiSoC implement their own bus, called LASMIbus, that features the last two techniques. Grouping by row had been previously explored with ASMI, but difficulties in achieving timing closure at reasonable latencies in FPGA combined with uncertain performance pay-off for some applications discouraged work in that direction.
Topology and transactions Topology and transactions
========================= =========================
The LASMI consists of one or several memory controllers (e.g. LASMIcon from milkymist-ng), multiple masters, and crossbar interconnect. The LASMI consists of one or several memory controllers (e.g. LASMIcon from MiSoC), multiple masters, and crossbar interconnect.
Each memory controller can expose several bank machines to the crossbar. This way, requests to different SDRAM banks can be processed in parallel. Each memory controller can expose several bank machines to the crossbar. This way, requests to different SDRAM banks can be processed in parallel.