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cores/video/VideoFrameBuffer: Add missing ClockDomainsRenamer on Converter (thanks @rdolbeau). 

Converter was not running in the right clock domain in ((dram_port.data_width > depth) and clock_faster_than_sys) case.
This commit is contained in:
Florent Kermarrec 2021-10-08 14:33:04 +02:00
parent f508b131ea
commit db20cb172d
1 changed files with 1 additions and 1 deletions
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litex/soc/cores/video.py
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@ -634,7 +634,7 @@ class VideoFrameBuffer(Module, AutoCSR):
self.submodules.cdc = stream.ClockDomainCrossing([("data", dram_port.data_width)], cd_from="sys", cd_to=clock_domain) self.submodules.cdc = stream.ClockDomainCrossing([("data", dram_port.data_width)], cd_from="sys", cd_to=clock_domain)
self.comb += self.dma.source.connect(self.cdc.sink) self.comb += self.dma.source.connect(self.cdc.sink)
# ... and then Data-Width Conversion. # ... and then Data-Width Conversion.
self.submodules.conv = stream.Converter(dram_port.data_width, depth) self.submodules.conv = ClockDomainsRenamer(clock_domain)(stream.Converter(dram_port.data_width, depth))
self.comb += self.cdc.source.connect(self.conv.sink) self.comb += self.cdc.source.connect(self.conv.sink)
video_pipe_source = self.conv.source video_pipe_source = self.conv.source
# Elsif DRAM Data Width <= depth or Video clock is slower than sys_clk: # Elsif DRAM Data Width <= depth or Video clock is slower than sys_clk: