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interconnect/wishbone: Add address_width property to make sure all interfaces (Wishbone/AXI-Lite/AXI) have it.

This commit is contained in:
Florent Kermarrec 2023-09-01 12:16:15 +02:00
parent 33efa09663
commit db2ad78860
1 changed files with 3 additions and 2 deletions
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5
litex/soc/interconnect/wishbone.py
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@ -50,8 +50,9 @@ class Interface(Record):
if kwargs.get("address_width", False):
# FIXME: Improve or switch Wishbone to byte addressing instead of word addressing.
adr_width = kwargs["address_width"] - int(log2(data_width//8))
self.adr_width = adr_width
self.bursting = bursting
self.adr_width = adr_width
self.address_width = adr_width + int(log2(data_width//8))
self.bursting = bursting
Record.__init__(self, set_layout_parameters(_layout,
adr_width = adr_width,
data_width = data_width,