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soc/cores/clock: also allow margin=0 on iCE40PLL and ECP5PLL

This commit is contained in:
Florent Kermarrec 2020-01-01 13:24:06 +01:00
parent caacc41103
commit db7a48c05d
1 changed files with 2 additions and 2 deletions
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4
litex/soc/cores/clock.py
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@ -448,7 +448,7 @@ class iCE40PLL(Module):
valid = False valid = False
for divq in range(*self.divq_range): for divq in range(*self.divq_range):
clk_freq = vco_freq/(2**divq) clk_freq = vco_freq/(2**divq)
if abs(clk_freq - f) < f*m: if abs(clk_freq - f) <= f*m:
config["divq"] = divq config["divq"] = divq
valid = True valid = True
break break
@ -541,7 +541,7 @@ class ECP5PLL(Module):
valid = False valid = False
for d in range(*self.clko_div_range): for d in range(*self.clko_div_range):
clk_freq = vco_freq/d clk_freq = vco_freq/d
if abs(clk_freq - f) < f*m: if abs(clk_freq - f) <= f*m:
config["clko{}_freq".format(n)] = clk_freq config["clko{}_freq".format(n)] = clk_freq
config["clko{}_div".format(n)] = d config["clko{}_div".format(n)] = d
config["clko{}_phase".format(n)] = p config["clko{}_phase".format(n)] = p