soc/cores/hyperbus: Better split parameters/signals and use intermediate dq_o/oe/i and rwds_o/oe/i signals.
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@ -67,6 +67,8 @@ class HyperRAM(LiteXModule):
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# Parameters.
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# -----------
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dw = len(pads.dq) if not hasattr(pads.dq, "oe") else len(pads.dq.o)
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assert dw in [8, 16]
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assert latency_mode in ["fixed", "variable"]
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# Internal Signals.
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@ -78,11 +80,28 @@ class HyperRAM(LiteXModule):
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ca_active = Signal()
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sr = Signal(48)
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sr_next = Signal(48)
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dq_o = Signal(dw)
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dq_oe = Signal()
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dq_i = Signal(dw)
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rwds_o = Signal(dw//8)
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rwds_oe = Signal()
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rwds_i = Signal(dw//8)
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# Tristates.
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# ----------
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dq = self.add_tristate(pads.dq) if not hasattr(pads.dq, "oe") else pads.dq
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rwds = self.add_tristate(pads.rwds) if not hasattr(pads.rwds, "oe") else pads.rwds
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dw = len(pads.dq) if not hasattr(pads.dq, "oe") else len(pads.dq.o)
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self.comb += [
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# DQ.
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dq.o.eq( dq_o),
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dq.oe.eq(dq_oe),
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dq_i.eq( dq.i),
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assert dw in [8, 16]
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# RWDS.
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rwds.o.eq( rwds_o),
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rwds.oe.eq(rwds_oe),
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rwds_i.eq( rwds.i),
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]
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# Drive Control Signals --------------------------------------------------------------------
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@ -122,7 +141,7 @@ class HyperRAM(LiteXModule):
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# Data Shift-In Register -------------------------------------------------------------------
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dqi = Signal(dw)
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self.sync += dqi.eq(dq.i) # Sample on 90° and 270° Clk Phases.
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self.sync += dqi.eq(dq_i) # Sample on 90° and 270° Clk Phases.
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self.comb += [
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sr_next.eq(Cat(dqi, sr[:-dw])),
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If(ca_active,
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@ -134,10 +153,10 @@ class HyperRAM(LiteXModule):
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# Data Shift-Out Register ------------------------------------------------------------------
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self.comb += [
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bus.dat_r.eq(sr_next),
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If(dq.oe,
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dq.o.eq(sr[-dw:]),
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If(dq_oe,
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dq_o.eq(sr[-dw:]),
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If(ca_active,
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dq.o.eq(sr[-8:]) # Only use 8-bit for Command/Address.
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dq_o.eq(sr[-8:]) # Only use 8-bit for Command/Address.
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)
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)
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]
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@ -219,7 +238,7 @@ class HyperRAM(LiteXModule):
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cs.eq(1),
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# Send Command on DQ.
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ca_active.eq(1),
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dq.oe.eq(1),
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dq_oe.eq(1),
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# Wait for 6*2 cycles...
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If(cycles == (6*2 - 1),
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If(reg_write_req,
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@ -227,7 +246,7 @@ class HyperRAM(LiteXModule):
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NextState("REG-WRITE-0")
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).Else(
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# Sample RWDS to know if 1X/2X Latency should be used (Refresh).
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NextValue(refresh, rwds.i | (latency_mode in ["fixed"])),
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NextValue(refresh, rwds_i | (latency_mode in ["fixed"])),
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NextState("WAIT-LATENCY")
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)
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)
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@ -237,7 +256,7 @@ class HyperRAM(LiteXModule):
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cs.eq(1),
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# Send Reg on DQ.
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ca_active.eq(1),
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dq.oe.eq(1),
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dq_oe.eq(1),
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# Wait for 2 cycles...
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If(cycles == (2 - 1),
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NextValue(sr, Cat(Signal(40), self.reg_write_data[:8])),
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@ -249,7 +268,7 @@ class HyperRAM(LiteXModule):
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cs.eq(1),
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# Send Reg on DQ.
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ca_active.eq(1),
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dq.oe.eq(1),
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dq_oe.eq(1),
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# Wait for 2 cycles...
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If(cycles == (2 - 1),
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reg_ep.ready.eq(1),
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@ -282,9 +301,9 @@ class HyperRAM(LiteXModule):
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ca_active.eq(reg_read_req),
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# Send Data on DQ/RWDS (for write).
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If(bus_we,
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dq.oe.eq(1),
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rwds.oe.eq(1),
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*[rwds.o[dw//8-1-i].eq(~bus_sel[4-1-n*dw//8-i]) for i in range(dw//8)],
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dq_oe.eq(1),
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rwds_oe.eq(1),
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*[rwds_o[dw//8-1-i].eq(~bus_sel[4-1-n*dw//8-i]) for i in range(dw//8)],
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),
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# Wait for 2 cycles (since HyperRAM's Clk = sys_clk/4).
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If(cycles == (2 - 1),
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