dvisampler: add HPD registers
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deb438ca18
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dba6189e38
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@ -3,7 +3,7 @@ from migen.fhdl.specials import Tristate
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from migen.genlib.cdc import MultiReg
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from migen.genlib.cdc import MultiReg
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from migen.genlib.fsm import FSM, NextState
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from migen.genlib.fsm import FSM, NextState
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from migen.genlib.misc import chooser
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from migen.genlib.misc import chooser
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from migen.bank.description import AutoCSR
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from migen.bank.description import CSRStorage, CSRStatus, AutoCSR
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_default_edid = [
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_default_edid = [
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0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x3D, 0x17, 0x32, 0x12, 0x2A, 0x6A, 0xBF, 0x00,
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0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x3D, 0x17, 0x32, 0x12, 0x2A, 0x6A, 0xBF, 0x00,
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@ -18,10 +18,21 @@ _default_edid = [
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class EDID(Module, AutoCSR):
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class EDID(Module, AutoCSR):
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def __init__(self, pads, default=_default_edid):
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def __init__(self, pads, default=_default_edid):
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self._r_hpd_notif = CSRStatus()
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self._r_hpd_en = CSRStorage()
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self.specials.mem = Memory(8, 128, init=default)
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self.specials.mem = Memory(8, 128, init=default)
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###
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###
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# HPD
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if hasattr(pads, "hpd_notif"):
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self.specials += MultiReg(pads.hpd_notif, self._r_hpd_notif.status)
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else:
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self.comb += self._r_hpd_notif.status.eq(1)
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if hasattr(pads, "hpd_en"):
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self.comb += pads.hpd_en.eq(self._r_hpd_en.storage)
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# EDID
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scl_raw = Signal()
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scl_raw = Signal()
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sda_i = Signal()
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sda_i = Signal()
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sda_drv = Signal()
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sda_drv = Signal()
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