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- init Repo
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Florent Kermarrec
commit
dbb363f039
2 changed files with 364 additions and 0 deletions
307
migScope/__init__.py
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307
migScope/__init__.py
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from migen.fhdl.structure import *
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from migen.bank import description, csrgen
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from migen.bank.description import READ_ONLY, WRITE_ONLY
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class Term:
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def __init__(self, width, pipe=False):
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self.width = width
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self.pipe = pipe
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self.i = Signal(BV(self.width))
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self.t = Signal(BV(self.width))
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self.o = Signal()
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def get_fragment(self):
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frag = [
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self.o.eq(self.i==self.t)
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]
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if self.pipe:
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return Fragment(sync=frag)
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else:
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return Fragment(comb=frag)
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class RangeDetector:
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def __init__(self, width, pipe=False):
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self.width = width
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self.pipe = pipe
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self.i = Signal(BV(self.width))
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self.low = Signal(BV(self.width))
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self.high = Signal(BV(self.width))
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self.o = Signal()
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def get_fragment(self):
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frag = [
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self.o.eq((self.i >= self.low) & ((self.i <= self.high)))
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]
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if self.pipe:
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return Fragment(sync=frag)
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else:
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return Fragment(comb=frag)
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class EdgeDetector:
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def __init__(self, width, pipe=False, mode = "RFB"):
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self.width = width
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self.pipe = pipe
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self.mode = mode
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self.i = Signal(BV(self.width))
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self.i_d = Signal(BV(self.width))
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if "R" in mode:
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self.r_mask = Signal(BV(self.width))
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self.ro = Signal()
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if "F" in mode:
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self.f_mask = Signal(BV(self.width))
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self.fo = Signal()
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if "B" in mode:
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self.b_mask = Signal(BV(self.width))
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self.bo = Signal()
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self.o = Signal()
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def get_fragment(self):
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comb = []
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sync = []
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sync += [self.i_d.eq(self.i)]
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# Rising Edge
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if "R" in self.mode:
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if self.pipe:
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sync += [self.ro.eq(self.i & (~self.i_d))]
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else:
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comb += [self.ro.eq(self.i & (~ self.i_d))]
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else:
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comb += [self.ro.eq(0)]
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# Falling Edge
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if "F" in self.mode:
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if self.pipe:
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sync += [self.fo.eq((~ self.i) & self.i_d)]
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else:
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comb += [self.fo.eq((~ self.i) & self.i_d)]
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else:
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comb += [self.fo.eq(0)]
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# Both
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if "B" in self.mode:
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if self.pipe:
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sync += [self.bo.eq(self.i != self.i_d)]
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else:
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comb += [self.bo.eq(self.i != self.i_d)]
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else:
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comb += [self.bo.eq(0)]
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#Output
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comb += [self.o.eq(self.ro | self.fo | self.bo)]
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return Fragment(comb, sync)
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class Timer:
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def __init__(self, width):
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self.width = width
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self.start = Signal()
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self.stop = Signal()
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self.clear = Signal()
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self.enable = Signal()
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self.cnt = Signal(BV(self.width))
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self.cnt_max = Signal(BV(self.width))
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self.o = Signal()
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def get_fragment(self):
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comb = []
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sync = []
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sync += [
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If(self.stop,
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self.enable.eq(0),
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self.cnt.eq(0),
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self.o.eq(0)
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).Elif(self.clear,
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self.cnt.eq(0),
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self.o.eq(0)
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).Elif(self.start,
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self.enable.eq(1)
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).Elif(self.enable,
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If(self.cnt <= self.cnt_max,
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self.cnt.eq(self.cnt+1)
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).Else(
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self.o.eq(1)
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)
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),
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If(self.enable,
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self.enable.eq(0),
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self.cnt.eq(0)
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).Elif(self.clear,
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self.cnt.eq(0)
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).Elif(self.start,
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self.enable.eq(1)
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)
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]
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return Fragment(comb, sync)
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class Sum:
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def __init__(self,size=4,pipe=False,prog_mode="PAR"):
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self.size = size
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self.pipe = pipe
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self.prog_mode = prog_mode
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assert (size <= 4), "size > 4 (This version support only non cascadable SRL16)"
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self.i0 = Signal()
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self.i1 = Signal()
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self.i2 = Signal()
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self.i3 = Signal()
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self._ce = Signal()
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self._shift_in = Signal()
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self.o = Signal()
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self._o = Signal()
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if self.prog_mode == "PAR":
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self.prog = Signal()
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self.prog_dat = Signal(BV(16))
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self._shift_dat = Signal(BV(17))
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self._shift_cnt = Signal(BV(4))
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elif self.prog_mode == "SHIFT":
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self.shift_ce = Signal()
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self.shift_in = Signal()
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self.shift_out = Signal()
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def get_fragment(self):
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_shift_out = Signal()
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comb = []
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sync = []
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if self.prog_mode == "PAR":
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sync += [
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If(self.prog,
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self._shift_dat.eq(self.prog_dat),
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self._shift_cnt.eq(16)
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),
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If(self._shift_cnt != 0,
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self._shift_dat.eq(self._shift_dat[1:]),
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self._shift_cnt.eq(self._shift_cnt-1),
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self._ce.eq(1)
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).Else(
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self._ce.eq(0)
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)
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]
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comb += [
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self._shift_in.eq(self._shift_dat[0])
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]
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elif self.prog_mode == "SHIFT":
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comb += [
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self._ce.eq(self.shift_ce),
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self._shift_in.eq(self.shift_in)
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]
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inst = [
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Instance("SRLC16E",
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[
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("a0", self.i0),
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("a1", self.i1),
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("a2", self.i2),
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("a3", self.i3),
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("ce", self._ce),
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("d", self._shift_in)
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] , [
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("q", self._o),
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("q15",_shift_out)
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] ,
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clkport="clk",
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)
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]
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if self.prog_mode == "SHIFT":
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comb += [
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self.shift_out.eq(_shift_out)
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]
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if self.pipe:
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sync += [self.o.eq(self._o)]
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else:
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comb += [self.o.eq(self._o)]
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return Fragment(comb=comb,sync=sync,instances=inst)
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class Recorder:
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def __init__(self, width, depth):
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self.width = width
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self.depth = depth
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self.depth_width = bits_for(self.depth)
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#Control
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self.rst = Signal()
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self.start = Signal()
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self.size = Signal(BV(self.depth_width))
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self.done = Signal()
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#Write Path
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self.put = Signal()
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self.put_dat = Signal(BV(self.width))
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self._put_cnt = Signal(BV(self.depth_width))
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self._put_ptr = Signal(BV(self.depth_width))
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self._put_port = MemoryPort(adr=self._put_ptr, we=self.put, dat_w=self.put_dat)
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#Read Path
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self.get = Signal()
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self.get_dat = Signal(BV(self.width))
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self._get_cnt = Signal(BV(self.depth_width))
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self._get_ptr = Signal(BV(self.depth_width))
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self._get_port = MemoryPort(adr=self._get_ptr, re=self.get, dat_r=self.get_dat)
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#Others
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self._mem = Memory(self.width, self.depth, self._put_port, self._get_port)
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def get_fragment(self):
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comb = []
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sync = []
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memories = [self._mem]
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#Control
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sync += [
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If(self.rst,
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self._put_cnt.eq(0),
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self._put_ptr.eq(0),
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self._get_cnt.eq(0),
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self._get_ptr.eq(0),
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self.done.eq(0)
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).Elif(self.start,
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self._put_cnt.eq(0),
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self._get_cnt.eq(0)
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),
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If(self.put,
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self._put_cnt.eq(self._put_cnt+1),
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self._put_ptr.eq(self._put_ptr+1)
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),
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If(self.get,
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self._get_cnt.eq(self._get_cnt+1),
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self._get_ptr.eq(self._get_ptr+1)
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)
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]
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comb += [
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If(self._put_cnt == self.size-1,
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self.done.eq(1)
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).Elif(self._get_cnt == self.size-1,
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self.done.eq(1)
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).Else(
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self.done.eq(0)
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)
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]
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return Fragment(comb=comb, sync=sync, memories=memories)
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class MigCon:
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pass
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class MigLa:
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pass
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class MigIo:
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def __init__(self, width, mode = "IO"):
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self.width = width
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self.mode = mode
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self.ireg = description.RegisterField("i", 0, READ_ONLY, WRITE_ONLY)
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self.oreg = description.RegisterField("o", 0)
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if "I" in self.mode:
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self.inputs = Signal(BV(self.width))
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self.ireg = description.RegisterField("i", self.width, READ_ONLY, WRITE_ONLY)
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self.ireg.field.w.name_override = "inputs"
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if "O" in self.mode:
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self.outputs = Signal(BV(self.width))
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self.oreg = description.RegisterField("o", self.width)
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self.oreg.field.r.name_override = "ouptuts"
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self.bank = csrgen.Bank([self.oreg, self.ireg])
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def get_fragment(self):
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return self.bank.get_fragment()
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57
top.py
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57
top.py
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@ -0,0 +1,57 @@
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from fractions import Fraction
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from math import ceil
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from migen.fhdl.structure import *
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from migen.fhdl import verilog, autofragment
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from migen.bus import csr
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import migScope
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#
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#Test RangeDetector
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#
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#term = migScope.Term(32,True)
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#v = verilog.convert(term.get_fragment())
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#print(v)
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#
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#Test RangeDetector
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#
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#rangeDetector = migScope.RangeDetector (32,True)
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#v = verilog.convert(rangeDetector.get_fragment())
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#print(v)
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#
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#Test EdgeDetector
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#
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#edgeDetector = migScope.EdgeDetector (32,True,"RFB")
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#v = verilog.convert(edgeDetector.get_fragment())
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#print(v)
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#
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#Test Timer
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#
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#timer = migScope.Timer(32)
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#v = verilog.convert(timer.get_fragment())
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#print(v)
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#
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#Test Sum
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#
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sum = migScope.Sum(4,pipe=True)
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v = verilog.convert(sum.get_fragment())
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print(v)
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#
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#Test MigIo
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#
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#migIo = migScope.MigIo(32,"IO")
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#v = verilog.convert(migIo.get_fragment())
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#print(v)
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#
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#Test Recorder
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#
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#recorder = migScope.Recorder(32,1024)
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#v = verilog.convert(recorder.get_fragment())
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#print(v)
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