bank/description/CSRStorage: support alignment bits
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51f1ace061
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@ -47,14 +47,17 @@ class CSRStatus(_CompoundCSR):
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self.simple_csrs.append(sc)
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class CSRStorage(_CompoundCSR):
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def __init__(self, size=1, reset=0, atomic_write=False, write_from_dev=False, name=None):
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def __init__(self, size=1, reset=0, atomic_write=False, write_from_dev=False, alignment_bits=0, name=None):
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_CompoundCSR.__init__(self, size, name)
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self.storage = Signal(self.size, reset=reset)
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self.alignment_bits = alignment_bits
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self.storage_full = Signal(self.size, reset=reset)
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self.storage = Signal(self.size - self.alignment_bits)
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self.comb += self.storage.eq(self.storage_full[self.alignment_bits:])
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self.atomic_write = atomic_write
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if write_from_dev:
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self.we = Signal()
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self.dat_w = Signal(self.size)
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self.sync += If(self.we, self.storage.eq(self.dat_w))
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self.dat_w = Signal(self.size - self.alignment_bits)
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self.sync += If(self.we, self.storage_full.eq(self.dat_w << self.alignment_bits))
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def do_finalize(self, busword):
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nwords = (self.size + busword - 1)//busword
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@ -63,20 +66,25 @@ class CSRStorage(_CompoundCSR):
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for i in reversed(range(nwords)):
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nbits = min(self.size - i*busword, busword)
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sc = CSR(nbits, self.name + str(i) if nwords else self.name)
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self.simple_csrs.append(sc)
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lo = i*busword
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hi = lo+nbits
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# read
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self.comb += sc.w.eq(self.storage[lo:hi])
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if lo >= self.alignment_bits:
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self.comb += sc.w.eq(self.storage_full[lo:hi])
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elif hi > self.alignment_bits:
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self.comb += sc.w.eq(Cat(Replicate(0, hi - self.alignment_bits),
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self.storage_full[self.alignment_bits:hi]))
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else:
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self.comb += sc.w.eq(0)
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# write
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if nwords > 1 and self.atomic_write:
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if i:
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self.sync += If(sc.re, backstore[lo-busword:hi-busword].eq(sc.r))
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else:
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self.sync += If(sc.re, self.storage.eq(Cat(sc.r, backstore)))
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self.sync += If(sc.re, self.storage_full.eq(Cat(sc.r, backstore)))
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else:
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self.sync += If(sc.re, self.storage[lo:hi].eq(sc.r))
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self.simple_csrs.append(sc)
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self.sync += If(sc.re, self.storage_full[lo:hi].eq(sc.r))
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def csrprefix(prefix, csrs):
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for csr in csrs:
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