soc_sdram: remove minicon support (we will make lasmicon more configurable to reduce ressource usage)
This commit is contained in:
Florent Kermarrec
parent
44d766c09f
commit
dc52d33fba
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@ -9,34 +9,26 @@ from litex.soc.integration.soc_core import *
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from litedram import lasmi_bus
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from litedram.frontend import wishbone2lasmi
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from litedram import dfii, minicon, lasmicon
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from litedram import dfii, lasmicon
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__all__ = ["SoCSDRAM", "soc_sdram_args", "soc_sdram_argdict"]
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class ControllerInjector(Module, AutoCSR):
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def __init__(self, phy, controller_type, geom_settings, timing_settings, controller_settings):
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def __init__(self, phy, geom_settings, timing_settings, controller_settings):
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self.submodules.dfii = dfii.DFIInjector(geom_settings.addressbits, geom_settings.bankbits,
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phy.settings.dfi_databits, phy.settings.nphases)
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self.comb += self.dfii.master.connect(phy.dfi)
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if controller_type == "lasmicon":
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self.submodules.controller = controller = lasmicon.LASMIcon(phy.settings,
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geom_settings,
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timing_settings,
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controller_settings)
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self.comb += controller.dfi.connect(self.dfii.slave)
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self.submodules.controller = controller = lasmicon.LASMIcon(phy.settings,
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geom_settings,
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timing_settings,
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controller_settings)
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self.comb += controller.dfi.connect(self.dfii.slave)
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self.submodules.crossbar = lasmi_bus.LASMIxbar([controller.lasmic],
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controller.nrowbits)
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elif controller_type == "minicon":
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self.submodules.controller = controller = minicon.Minicon(phy.settings,
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geom_settings,
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timing_settings)
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self.comb += controller.dfi.connect(self.dfii.slave)
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else:
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raise ValueError("Unsupported SDRAM controller type")
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self.submodules.crossbar = lasmi_bus.LASMIxbar([controller.lasmic],
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controller.nrowbits)
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class SoCSDRAM(SoCCore):
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@ -59,12 +51,12 @@ class SoCSDRAM(SoCCore):
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raise FinalizeError
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self._wb_sdram_ifs.append(interface)
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def register_sdram(self, phy, sdram_controller_type, geom_settings, timing_settings, controller_settings=None):
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def register_sdram(self, phy, geom_settings, timing_settings, controller_settings=None):
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assert not self._sdram_phy
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self._sdram_phy.append(phy) # encapsulate in list to prevent CSR scanning
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self.submodules.sdram = ControllerInjector(
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phy, sdram_controller_type, geom_settings, timing_settings, controller_settings)
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phy, geom_settings, timing_settings, controller_settings)
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dfi_databits_divisor = 1 if phy.settings.memtype == "SDR" else 2
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sdram_width = phy.settings.dfi_databits//dfi_databits_divisor
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@ -80,36 +72,19 @@ class SoCSDRAM(SoCCore):
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self.add_wb_sdram_if(wb_sdram)
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self.register_mem("main_ram", self.mem_map["main_ram"], wb_sdram, main_ram_size)
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if sdram_controller_type == "lasmicon":
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if self.l2_size:
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lasmim = self.sdram.crossbar.get_master()
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l2_cache = wishbone.Cache(self.l2_size//4, self._wb_sdram, wishbone.Interface(lasmim.dw))
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# XXX Vivado ->2015.1 workaround, Vivado is not able to map correctly our L2 cache.
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# Issue is reported to Xilinx and should be fixed in next releases (2015.2?).
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# Remove this workaround when fixed by Xilinx.
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from litex.build.xilinx.vivado import XilinxVivadoToolchain
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if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
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from litex.gen.fhdl.simplify import FullMemoryWE
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self.submodules.l2_cache = FullMemoryWE()(l2_cache)
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else:
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self.submodules.l2_cache = l2_cache
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self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_cache.slave, lasmim)
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elif sdram_controller_type == "minicon":
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if self.l2_size:
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l2_cache = wishbone.Cache(self.l2_size//4, self._wb_sdram, self.sdram.controller.bus)
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# XXX Vivado ->2015.1 workaround, Vivado is not able to map correctly our L2 cache.
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# Issue is reported to Xilinx and should be fixed in next releases (2015.2?).
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# Remove this workaround when fixed by Xilinx.
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from litex.build.xilinx.vivado import XilinxVivadoToolchain
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if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
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from litex.gen.fhdl.simplify import FullMemoryWE
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self.submodules.l2_cache = FullMemoryWE()(l2_cache)
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else:
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self.submodules.l2_cache = l2_cache
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if self.l2_size:
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lasmim = self.sdram.crossbar.get_master()
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l2_cache = wishbone.Cache(self.l2_size//4, self._wb_sdram, wishbone.Interface(lasmim.dw))
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# XXX Vivado ->2015.1 workaround, Vivado is not able to map correctly our L2 cache.
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# Issue is reported to Xilinx and should be fixed in next releases (2015.2?).
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# Remove this workaround when fixed by Xilinx.
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from litex.build.xilinx.vivado import XilinxVivadoToolchain
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if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
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from litex.gen.fhdl.simplify import FullMemoryWE
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self.submodules.l2_cache = FullMemoryWE()(l2_cache)
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else:
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self.submodules.converter = wishbone.Converter(self._wb_sdram, self.sdram.controller.bus)
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else:
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raise ValueError
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self.submodules.l2_cache = l2_cache
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self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_cache.slave, lasmim)
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def do_finalize(self):
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if not self.integrated_main_ram_size:
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