build.xilinx: Run `phys_opt_design` and generate timing report.
Makes the flow more similar to migen.
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@ -147,6 +147,8 @@ class XilinxVivadoToolchain:
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tcl.append("report_control_sets -verbose -file {}_control_sets.rpt".format(build_name))
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tcl.append("report_clock_utilization -file {}_clock_utilization.rpt".format(build_name))
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tcl.append("route_design")
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tcl.append("phys_opt_design")
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tcl.append("report_timing_summary -no_header -no_detailed_paths")
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tcl.append("write_checkpoint -force {}_route.dcp".format(build_name))
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tcl.append("report_route_status -file {}_route_status.rpt".format(build_name))
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tcl.append("report_drc -file {}_drc.rpt".format(build_name))
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