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build.xilinx: Run `phys_opt_design` and generate timing report. 

Makes the flow more similar to migen.
This commit is contained in:
Tim 'mithro' Ansell 2018-10-03 16:02:43 -07:00
parent 948527b0fe
commit dc7cd75757
1 changed files with 2 additions and 0 deletions
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2
litex/build/xilinx/vivado.py
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@ -147,6 +147,8 @@ class XilinxVivadoToolchain:
tcl.append("report_control_sets -verbose -file {}_control_sets.rpt".format(build_name)) tcl.append("report_control_sets -verbose -file {}_control_sets.rpt".format(build_name))
tcl.append("report_clock_utilization -file {}_clock_utilization.rpt".format(build_name)) tcl.append("report_clock_utilization -file {}_clock_utilization.rpt".format(build_name))
tcl.append("route_design") tcl.append("route_design")
tcl.append("phys_opt_design")
tcl.append("report_timing_summary -no_header -no_detailed_paths")
tcl.append("write_checkpoint -force {}_route.dcp".format(build_name)) tcl.append("write_checkpoint -force {}_route.dcp".format(build_name))
tcl.append("report_route_status -file {}_route_status.rpt".format(build_name)) tcl.append("report_route_status -file {}_route_status.rpt".format(build_name))
tcl.append("report_drc -file {}_drc.rpt".format(build_name)) tcl.append("report_drc -file {}_drc.rpt".format(build_name))