[fix] Slave interface HP0 clk name

2019-07-12 16:37:23 +02:00 · 2019-07-12 16:37:23 +02:00 · dcf55ad4f3
parent be280bed5e
commit dcf55ad4f3
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/integration/soc_zynq.py
+++ b/litex/soc/integration/soc_zynq.py
@ -142,7 +142,7 @@ class SoCZynq(SoCCore):
        self.axi_hp0_fifo_ctrl = axi_hp0_fifo_ctrl = Record(axi_fifo_ctrl_layout())
        self.ps7_params.update(
            # axi hp0 clk
-            i_M_AXI_HP0_ACLK=ClockSignal("sys"),
+            i_S_AXI_HP0_ACLK=ClockSignal("sys"),

            # axi hp0 aw
            i_S_AXI_HP0_AWVALID=axi_hp0.aw.valid,