Merge pull request #1993 from FlyGoat/jtag-patch

Expand litex_sim JTAG support to more CPUs

litex/build/sim/core/modules/jtagremote/jtagremote.c

@@ -15,6 +15,7 @@ struct session_s {
 	char *tdo;
 	char *tck;
 	char *tms;
+	char *ntrst;
 	char *sys_clk;
 	struct event *ev;
 	char databuf[2048];
@@ -199,6 +200,7 @@ static int jtagremote_add_pads(void *sess, struct pad_list_s *plist)
     litex_sim_module_pads_get(pads, "tdi", (void**)&s->tdi);
     litex_sim_module_pads_get(pads, "tdo", (void**)&s->tdo);
     litex_sim_module_pads_get(pads, "tms", (void**)&s->tms);
+    litex_sim_module_pads_get(pads, "ntrst", (void**)&s->ntrst);
   }
 
   if(!strcmp(plist->name, "sys_clk"))
@@ -227,19 +229,34 @@ static int jtagremote_tick(void *sess, uint64_t time_ps)
   {
 	  c = s->databuf[s->data_start];
 
-	  if((c >= '0') && (c <= '7')){
-		  *s->tck = ((c - '0') >> 2) & 1;
-		  *s->tms = ((c - '0') >> 1) & 1;
-		  *s->tdi = (c - '0')  & 1;
-	  }
-	  if(c == 'R'){
-		  val = *s->tdo + '0';
-		  if(-1 == write(s->fd, &val, 1)) {
-			  eprintf("Error writing on socket\n");
-			  ret = RC_ERROR;
-			  goto out;
-		  }
+	  switch(c) {
+	  case '0'...'7':
+		*s->tck = ((c - '0') >> 2) & 1;
+		*s->tms = ((c - '0') >> 1) & 1;
+		*s->tdi = (c - '0')  & 1;
+		break;
+	  case 'r':
+	  case 's':
+		/* Deassert reset */
+		*s->ntrst = 1;
+		break;
+	  case 't':
+	  case 'u':
+		/* Assert reset */
+		*s->ntrst = 0;
+		break;
+	  case 'R':
+		val = *s->tdo + '0';
+		if(write(s->fd, &val, 1) == -1) {
+			eprintf("Error writing on socket\n");
+			ret = RC_ERROR;
+			goto out;
+		}
+		break;
+	  default:
+		break;
 	  }
+
 	  s->data_start = (s->data_start + 1) % 2048;
 	  s->datalen--;
   }

litex/soc/cores/cpu/naxriscv/core.py

@@ -462,6 +462,14 @@ class NaxRiscv(CPU):
 
         self.soc_bus = soc.bus # FIXME: Save SoC Bus instance to retrieve the final mem layout on finalization.
 
+    def add_jtag(self, pads):
+        self.comb += [
+            self.jtag_tms.eq(pads.tms),
+            self.jtag_clk.eq(pads.tck),
+            self.jtag_tdi.eq(pads.tdi),
+            pads.tdo.eq(self.jtag_tdo),
+        ]
+
     def add_memory_buses(self, address_width, data_width):
         NaxRiscv.litedram_width = data_width
         nax_data_width = 64

litex/soc/cores/cpu/vexiiriscv/core.py

@@ -527,6 +527,14 @@ class VexiiRiscv(CPU):
             i_mBus_rlast     = mbus.r.last,
         )
 
+    def add_jtag(self, pads):
+        self.comb += [
+            self.jtag_tms.eq(pads.tms),
+            self.jtag_clk.eq(pads.tck),
+            self.jtag_tdi.eq(pads.tdi),
+            pads.tdo.eq(self.jtag_tdo),
+        ]
+
     def do_finalize(self):
         assert hasattr(self, "reset_address")
 

litex/soc/cores/cpu/vexriscv_smp/core.py

@@ -463,6 +463,14 @@ class VexRiscvSMP(CPU):
         add_synthesis_define(cluster_filename)
         platform.add_source(cluster_filename, "verilog")
 
+    def add_jtag(self, pads):
+        self.comb += [
+            self.jtag_tms.eq(pads.tms),
+            self.jtag_clk.eq(pads.tck),
+            self.jtag_tdi.eq(pads.tdi),
+            pads.tdo.eq(self.jtag_tdo),
+        ]
+
     def add_soc_components(self, soc):
         if self.variant == "linux":
             # Set UART/Timer0 CSRs to the ones used by OpenSBI.

litex/tools/litex_sim.py

@@ -135,6 +135,7 @@ _io = [
         Subsignal("tms", Pins(1)),
         Subsignal("tdi", Pins(1)),
         Subsignal("tdo", Pins(1)),
+        Subsignal("ntrst", Pins(1)),
     ),
 
     # Video (VGA).
@@ -277,10 +278,7 @@ class SimSoC(SoCCore):
         # JTAG -------------------------------------------------------------------------------------
         if with_jtag:
             jtag_pads = platform.request("jtag")
-            self.comb += self.cpu.jtag_clk.eq(jtag_pads.tck)
-            self.comb += self.cpu.jtag_tms.eq(jtag_pads.tms)
-            self.comb += self.cpu.jtag_tdi.eq(jtag_pads.tdi)
-            self.comb += jtag_pads.tdo.eq(self.cpu.jtag_tdo)
+            self.cpu.add_jtag(jtag_pads)
 
         # SDCard -----------------------------------------------------------------------------------
         if with_sdcard: