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cpu/openc906: add ethmac to memory map and misc changes 

The default ethmac section address conflicts with main_ram defined for
openC906.

Add a custom position of ethmac to the memory map, which directly
follows the internal APB.

Also fix the start address of checked IO region from 0xa0000000 to
the full Region 1 in sysmap.h, and add plic and clint sections like
other RISC-V CPU cores (although they're internal to the CPU and won't
be usable by LiteX).

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
This commit is contained in:
Icenowy Zheng 2022-11-03 15:44:09 +08:00
parent eb2e9a371d
commit dd6e4868f2
1 changed files with 12 additions and 2 deletions
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14
litex/soc/cores/cpu/openc906/core.py
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@ -40,7 +40,7 @@ class OpenC906(CPU):
gcc_triple = CPU_GCC_TRIPLE_RISCV64 gcc_triple = CPU_GCC_TRIPLE_RISCV64
linker_output_format = "elf64-littleriscv" linker_output_format = "elf64-littleriscv"
nop = "nop" nop = "nop"
io_regions = {0xa000_0000: 0x2000_0000} # Origin, Length. io_regions = {0x9000_0000: 0x3000_0000} # Origin, Length.
# GCC Flags. # GCC Flags.
@property @property
@ -59,7 +59,11 @@ class OpenC906(CPU):
"main_ram": 0x0000_0000, # Region 0, Cacheable, Bufferable "main_ram": 0x0000_0000, # Region 0, Cacheable, Bufferable
"rom": 0x8000_0000, # Region 0 too "rom": 0x8000_0000, # Region 0 too
"sram": 0x8800_0000, # Region 0 too "sram": 0x8800_0000, # Region 0 too
# "internal_apb": 0x9000_0000, Region 1, Strong Order, Non-cacheable, Non-bufferable # By default, internal APB (contains PLIC and CLINT) is mapped at 0x9000_0000
# Internal APB has a fixed size of 0x800_0000
"plic": 0x9000_0000, # Region 1, Strong Order, Non-cacheable, Non-bufferable
"clint": 0x9400_0000, # Region 1 too
"ethmac": 0x9800_0000, # Region 1 too
"csr": 0xa000_0000, # Region 1 too "csr": 0xa000_0000, # Region 1 too
} }
@ -156,6 +160,12 @@ class OpenC906(CPU):
# Import a filelist for generic platforms # Import a filelist for generic platforms
add_manifest_sources(platform, "gen_rtl/filelists/generic_fpga.fl") add_manifest_sources(platform, "gen_rtl/filelists/generic_fpga.fl")
def add_soc_components(self, soc, soc_region_cls):
plic = soc_region_cls(origin=soc.mem_map.get("plic"), size=0x400_0000, cached=False)
clint = soc_region_cls(origin=soc.mem_map.get("clint"), size=0x400_0000, cached=False)
soc.bus.add_region(name="plic", region=plic)
soc.bus.add_region(name="clint", region=clint)
def set_reset_address(self, reset_address): def set_reset_address(self, reset_address):
self.reset_address = reset_address self.reset_address = reset_address
self.cpu_params.update(i_pad_cpu_rvba=Signal(40, reset=reset_address)) self.cpu_params.update(i_pad_cpu_rvba=Signal(40, reset=reset_address))