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Remove uses of the RE signal on field registers

This commit is contained in:
Sebastien Bourdeauducq 2012-10-09 19:08:37 +02:00
parent c86dd3cbef
commit dd6eacba62
4 changed files with 69 additions and 54 deletions
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9
milkymist/dfii/__init__.py
View File

@ -15,6 +15,7 @@ class PhaseInjector:
self._rden = Field("rden", 1, WRITE_ONLY, READ_ONLY) self._rden = Field("rden", 1, WRITE_ONLY, READ_ONLY)
self._command = RegisterFields("command", self._command = RegisterFields("command",
[self._cs, self._we, self._cas, self._ras, self._wren, self._rden]) [self._cs, self._we, self._cas, self._ras, self._wren, self._rden])
self._command_issue = RegisterRaw("command_issue")
self._address = RegisterField("address", len(self.phase.address)) self._address = RegisterField("address", len(self.phase.address))
self._baddress = RegisterField("baddress", len(self.phase.bank)) self._baddress = RegisterField("baddress", len(self.phase.bank))
@ -23,13 +24,13 @@ class PhaseInjector:
self._rddata = RegisterField("rddata", len(self.phase.rddata), READ_ONLY, WRITE_ONLY) self._rddata = RegisterField("rddata", len(self.phase.rddata), READ_ONLY, WRITE_ONLY)
def get_registers(self): def get_registers(self):
return [self._command, return [self._command, self._command_issue,
self._address, self._baddress, self._address, self._baddress,
self._wrdata, self._rddata] self._wrdata, self._rddata]
def get_fragment(self): def get_fragment(self):
comb = [ comb = [
If(self._command.re, If(self._command_issue.re,
self.phase.cs_n.eq(~self._cs.r), self.phase.cs_n.eq(~self._cs.r),
self.phase.we_n.eq(~self._we.r), self.phase.we_n.eq(~self._we.r),
self.phase.cas_n.eq(~self._cas.r), self.phase.cas_n.eq(~self._cas.r),
@ -42,8 +43,8 @@ class PhaseInjector:
), ),
self.phase.address.eq(self._address.field.r), self.phase.address.eq(self._address.field.r),
self.phase.bank.eq(self._baddress.field.r), self.phase.bank.eq(self._baddress.field.r),
self.phase.wrdata_en.eq(self._command.re & self._wren.r), self.phase.wrdata_en.eq(self._command_issue.re & self._wren.r),
self.phase.rddata_en.eq(self._command.re & self._rden.r), self.phase.rddata_en.eq(self._command_issue.re & self._rden.r),
self.phase.wrdata.eq(self._wrdata.field.r), self.phase.wrdata.eq(self._wrdata.field.r),
self.phase.wrdata_mask.eq(0) self.phase.wrdata_mask.eq(0)
] ]

2
milkymist/minimac3/__init__.py
View File

@ -26,7 +26,7 @@ class MiniMAC:
self._rx_count_0 = RegisterField("rx_count_0", _count_width, access_bus=READ_ONLY, access_dev=WRITE_ONLY) self._rx_count_0 = RegisterField("rx_count_0", _count_width, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
self._rx_count_1 = RegisterField("rx_count_1", _count_width, access_bus=READ_ONLY, access_dev=WRITE_ONLY) self._rx_count_1 = RegisterField("rx_count_1", _count_width, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
self._tx_count = RegisterField("tx_count", _count_width, access_dev=READ_WRITE) self._tx_count = RegisterField("tx_count", _count_width, access_dev=READ_WRITE)
self._tx_start = RegisterField("tx_start", access_bus=WRITE_ONLY) self._tx_start = RegisterRaw("tx_start")
regs = [self._phy_reset, self._rx_count_0, self._rx_count_1, self._tx_count, self._tx_start] regs = [self._phy_reset, self._rx_count_0, self._rx_count_1, self._tx_count, self._tx_start]
self._rx_event_0 = EventSourcePulse() self._rx_event_0 = EventSourcePulse()

32
software/bios/sdram.c
View File

@ -23,6 +23,18 @@ static void setaddr(int a)
CSR_DFII_AL_P1 = a & 0x00ff; CSR_DFII_AL_P1 = a & 0x00ff;
} }
static void command_p0(int cmd)
{
CSR_DFII_COMMAND_P0 = cmd;
CSR_DFII_COMMAND_ISSUE_P0 = 1;
}
static void command_p1(int cmd)
{
CSR_DFII_COMMAND_P1 = cmd;
CSR_DFII_COMMAND_ISSUE_P1 = 1;
}
static void init_sequence(void) static void init_sequence(void)
{ {
int i; int i;
@ -34,33 +46,33 @@ static void init_sequence(void)
/* Precharge All */ /* Precharge All */
setaddr(0x0400); setaddr(0x0400);
CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS; command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
/* Load Extended Mode Register */ /* Load Extended Mode Register */
CSR_DFII_BA_P0 = 1; CSR_DFII_BA_P0 = 1;
setaddr(0x0000); setaddr(0x0000);
CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS; command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
CSR_DFII_BA_P0 = 0; CSR_DFII_BA_P0 = 0;
/* Load Mode Register */ /* Load Mode Register */
setaddr(0x0132); /* Reset DLL, CL=3, BL=4 */ setaddr(0x0132); /* Reset DLL, CL=3, BL=4 */
CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS; command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
cdelay(200); cdelay(200);
/* Precharge All */ /* Precharge All */
setaddr(0x0400); setaddr(0x0400);
CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS; command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
/* 2x Auto Refresh */ /* 2x Auto Refresh */
for(i=0;i<2;i++) { for(i=0;i<2;i++) {
setaddr(0); setaddr(0);
CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS; command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS);
cdelay(4); cdelay(4);
} }
/* Load Mode Register */ /* Load Mode Register */
setaddr(0x0032); /* CL=3, BL=4 */ setaddr(0x0032); /* CL=3, BL=4 */
CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS; command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
cdelay(200); cdelay(200);
} }
@ -84,7 +96,7 @@ void ddrrow(char *_row)
if(*_row == 0) { if(*_row == 0) {
setaddr(0x0000); setaddr(0x0000);
CSR_DFII_BA_P0 = 0; CSR_DFII_BA_P0 = 0;
CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS; command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
cdelay(15); cdelay(15);
printf("Precharged\n"); printf("Precharged\n");
} else { } else {
@ -95,7 +107,7 @@ void ddrrow(char *_row)
} }
setaddr(row); setaddr(row);
CSR_DFII_BA_P0 = 0; CSR_DFII_BA_P0 = 0;
CSR_DFII_COMMAND_P0 = DFII_COMMAND_RAS|DFII_COMMAND_CS; command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CS);
cdelay(15); cdelay(15);
printf("Activated row %d\n", row); printf("Activated row %d\n", row);
} }
@ -119,7 +131,7 @@ void ddrrd(char *startaddr)
setaddr(addr); setaddr(addr);
CSR_DFII_BA_P0 = 0; CSR_DFII_BA_P0 = 0;
CSR_DFII_COMMAND_P0 = DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA; command_p0(DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA);
cdelay(15); cdelay(15);
for(i=0;i<8;i++) for(i=0;i<8;i++)
@ -152,7 +164,7 @@ void ddrwr(char *startaddr)
setaddr(addr); setaddr(addr);
CSR_DFII_BA_P1 = 0; CSR_DFII_BA_P1 = 0;
CSR_DFII_COMMAND_P1 = DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS|DFII_COMMAND_WRDATA; command_p1(DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS|DFII_COMMAND_WRDATA);
} }
#define TEST_SIZE (4*1024*1024) #define TEST_SIZE (4*1024*1024)

80
software/include/hw/dfii.h
View File

@ -12,46 +12,48 @@
#define DFII_CONTROL_CKE 0x02 #define DFII_CONTROL_CKE 0x02
#define CSR_DFII_COMMAND_P0 DFII_CSR(0x04) #define CSR_DFII_COMMAND_P0 DFII_CSR(0x04)
#define CSR_DFII_AH_P0 DFII_CSR(0x08) #define CSR_DFII_COMMAND_ISSUE_P0 DFII_CSR(0x08)
#define CSR_DFII_AL_P0 DFII_CSR(0x0C) #define CSR_DFII_AH_P0 DFII_CSR(0x0C)
#define CSR_DFII_BA_P0 DFII_CSR(0x10) #define CSR_DFII_AL_P0 DFII_CSR(0x10)
#define CSR_DFII_WD0_P0 DFII_CSR(0x14) #define CSR_DFII_BA_P0 DFII_CSR(0x14)
#define CSR_DFII_WD1_P0 DFII_CSR(0x18) #define CSR_DFII_WD0_P0 DFII_CSR(0x18)
#define CSR_DFII_WD2_P0 DFII_CSR(0x1C) #define CSR_DFII_WD1_P0 DFII_CSR(0x1C)
#define CSR_DFII_WD3_P0 DFII_CSR(0x20) #define CSR_DFII_WD2_P0 DFII_CSR(0x20)
#define CSR_DFII_WD4_P0 DFII_CSR(0x24) #define CSR_DFII_WD3_P0 DFII_CSR(0x24)
#define CSR_DFII_WD5_P0 DFII_CSR(0x28) #define CSR_DFII_WD4_P0 DFII_CSR(0x28)
#define CSR_DFII_WD6_P0 DFII_CSR(0x2C) #define CSR_DFII_WD5_P0 DFII_CSR(0x2C)
#define CSR_DFII_WD7_P0 DFII_CSR(0x30) #define CSR_DFII_WD6_P0 DFII_CSR(0x30)
#define CSR_DFII_RD0_P0 DFII_CSR(0x34) #define CSR_DFII_WD7_P0 DFII_CSR(0x34)
#define CSR_DFII_RD1_P0 DFII_CSR(0x38) #define CSR_DFII_RD0_P0 DFII_CSR(0x38)
#define CSR_DFII_RD2_P0 DFII_CSR(0x3C) #define CSR_DFII_RD1_P0 DFII_CSR(0x3C)
#define CSR_DFII_RD3_P0 DFII_CSR(0x40) #define CSR_DFII_RD2_P0 DFII_CSR(0x40)
#define CSR_DFII_RD4_P0 DFII_CSR(0x44) #define CSR_DFII_RD3_P0 DFII_CSR(0x44)
#define CSR_DFII_RD5_P0 DFII_CSR(0x48) #define CSR_DFII_RD4_P0 DFII_CSR(0x48)
#define CSR_DFII_RD6_P0 DFII_CSR(0x4C) #define CSR_DFII_RD5_P0 DFII_CSR(0x4C)
#define CSR_DFII_RD7_P0 DFII_CSR(0x50) #define CSR_DFII_RD6_P0 DFII_CSR(0x50)
#define CSR_DFII_RD7_P0 DFII_CSR(0x54)
#define CSR_DFII_COMMAND_P1 DFII_CSR(0x54) #define CSR_DFII_COMMAND_P1 DFII_CSR(0x58)
#define CSR_DFII_AH_P1 DFII_CSR(0x58) #define CSR_DFII_COMMAND_ISSUE_P1 DFII_CSR(0x5C)
#define CSR_DFII_AL_P1 DFII_CSR(0x5C) #define CSR_DFII_AH_P1 DFII_CSR(0x60)
#define CSR_DFII_BA_P1 DFII_CSR(0x60) #define CSR_DFII_AL_P1 DFII_CSR(0x64)
#define CSR_DFII_WD0_P1 DFII_CSR(0x64) #define CSR_DFII_BA_P1 DFII_CSR(0x68)
#define CSR_DFII_WD1_P1 DFII_CSR(0x68) #define CSR_DFII_WD0_P1 DFII_CSR(0x6C)
#define CSR_DFII_WD2_P1 DFII_CSR(0x6C) #define CSR_DFII_WD1_P1 DFII_CSR(0x70)
#define CSR_DFII_WD3_P1 DFII_CSR(0x70) #define CSR_DFII_WD2_P1 DFII_CSR(0x74)
#define CSR_DFII_WD4_P1 DFII_CSR(0x74) #define CSR_DFII_WD3_P1 DFII_CSR(0x78)
#define CSR_DFII_WD5_P1 DFII_CSR(0x78) #define CSR_DFII_WD4_P1 DFII_CSR(0x7C)
#define CSR_DFII_WD6_P1 DFII_CSR(0x7C) #define CSR_DFII_WD5_P1 DFII_CSR(0x80)
#define CSR_DFII_WD7_P1 DFII_CSR(0x80) #define CSR_DFII_WD6_P1 DFII_CSR(0x84)
#define CSR_DFII_RD0_P1 DFII_CSR(0x84) #define CSR_DFII_WD7_P1 DFII_CSR(0x88)
#define CSR_DFII_RD1_P1 DFII_CSR(0x88) #define CSR_DFII_RD0_P1 DFII_CSR(0x8C)
#define CSR_DFII_RD2_P1 DFII_CSR(0x8C) #define CSR_DFII_RD1_P1 DFII_CSR(0x90)
#define CSR_DFII_RD3_P1 DFII_CSR(0x90) #define CSR_DFII_RD2_P1 DFII_CSR(0x94)
#define CSR_DFII_RD4_P1 DFII_CSR(0x94) #define CSR_DFII_RD3_P1 DFII_CSR(0x98)
#define CSR_DFII_RD5_P1 DFII_CSR(0x98) #define CSR_DFII_RD4_P1 DFII_CSR(0x9C)
#define CSR_DFII_RD6_P1 DFII_CSR(0x9C) #define CSR_DFII_RD5_P1 DFII_CSR(0xA0)
#define CSR_DFII_RD7_P1 DFII_CSR(0xA0) #define CSR_DFII_RD6_P1 DFII_CSR(0xA4)
#define CSR_DFII_RD7_P1 DFII_CSR(0xA8)
#define DFII_COMMAND_CS 0x01 #define DFII_COMMAND_CS 0x01
#define DFII_COMMAND_WE 0x02 #define DFII_COMMAND_WE 0x02