soc_core: simplify settings (assume CPU and CSR present)
This commit is contained in:
Sebastien Bourdeauducq
parent
b1a90053f5
commit
dd7dfb0d5e
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@ -36,7 +36,7 @@ class SoCCore(Module):
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integrated_sram_size=4096,
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integrated_main_ram_size=0,
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shadow_base=0x80000000,
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with_csr=True, csr_data_width=8, csr_address_width=14,
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csr_data_width=8, csr_address_width=14,
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with_uart=True, uart_baudrate=115200,
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with_identifier=True,
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with_timer=True):
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@ -59,7 +59,6 @@ class SoCCore(Module):
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self.shadow_base = shadow_base
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self.with_csr = with_csr
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self.csr_data_width = csr_data_width
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self.csr_address_width = csr_address_width
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@ -70,51 +69,42 @@ class SoCCore(Module):
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self._wb_masters = []
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self._wb_slaves = []
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if cpu_type != "none":
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if cpu_type == "lm32":
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self.add_cpu_or_bridge(lm32.LM32(platform, self.cpu_reset_address))
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elif cpu_type == "or1k":
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self.add_cpu_or_bridge(mor1kx.MOR1KX(platform, self.cpu_reset_address))
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else:
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raise ValueError("Unsupported CPU type: {}".format(cpu_type))
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self.add_wb_master(self.cpu_or_bridge.ibus)
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self.add_wb_master(self.cpu_or_bridge.dbus)
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if cpu_type == "lm32":
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self.submodules.cpu = lm32.LM32(platform, self.cpu_reset_address)
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elif cpu_type == "or1k":
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self.submodules.cpu = mor1kx.MOR1KX(platform, self.cpu_reset_address)
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else:
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raise ValueError("Unsupported CPU type: {}".format(cpu_type))
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self.add_wb_master(self.cpu.ibus)
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self.add_wb_master(self.cpu.dbus)
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if integrated_rom_size:
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self.submodules.rom = wishbone.SRAM(integrated_rom_size, read_only=True)
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self.register_rom(self.rom.bus, integrated_rom_size)
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if integrated_rom_size:
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self.submodules.rom = wishbone.SRAM(integrated_rom_size, read_only=True)
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self.register_rom(self.rom.bus, integrated_rom_size)
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if integrated_sram_size:
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self.submodules.sram = wishbone.SRAM(integrated_sram_size)
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self.register_mem("sram", self.mem_map["sram"], self.sram.bus, integrated_sram_size)
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if integrated_sram_size:
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self.submodules.sram = wishbone.SRAM(integrated_sram_size)
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self.register_mem("sram", self.mem_map["sram"], self.sram.bus, integrated_sram_size)
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# Note: Main Ram can be used when no external SDRAM is available and use SDRAM mapping.
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if integrated_main_ram_size:
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self.submodules.main_ram = wishbone.SRAM(integrated_main_ram_size)
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self.register_mem("main_ram", self.mem_map["main_ram"], self.main_ram.bus, integrated_main_ram_size)
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# Note: Main Ram can be used when no external SDRAM is available and use SDRAM mapping.
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if integrated_main_ram_size:
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self.submodules.main_ram = wishbone.SRAM(integrated_main_ram_size)
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self.register_mem("main_ram", self.mem_map["main_ram"], self.main_ram.bus, integrated_main_ram_size)
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if with_csr:
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self.submodules.wishbone2csr = wishbone2csr.WB2CSR(
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bus_csr=csr_bus.Interface(csr_data_width, csr_address_width))
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self.register_mem("csr", self.mem_map["csr"], self.wishbone2csr.wishbone)
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self.submodules.wishbone2csr = wishbone2csr.WB2CSR(
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bus_csr=csr_bus.Interface(csr_data_width, csr_address_width))
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self.register_mem("csr", self.mem_map["csr"], self.wishbone2csr.wishbone)
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if with_uart:
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self.submodules.uart_phy = uart.RS232PHY(platform.request("serial"), clk_freq, uart_baudrate)
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self.submodules.uart = uart.UART(self.uart_phy)
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if with_uart:
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self.submodules.uart_phy = uart.RS232PHY(platform.request("serial"), clk_freq, uart_baudrate)
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self.submodules.uart = uart.UART(self.uart_phy)
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if with_identifier:
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platform_id = 0x554E if not hasattr(platform, "identifier") else platform.identifier
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self.submodules.identifier = identifier.Identifier(platform_id, int(clk_freq))
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if with_identifier:
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platform_id = 0x554E if not hasattr(platform, "identifier") else platform.identifier
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self.submodules.identifier = identifier.Identifier(platform_id, int(clk_freq))
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if with_timer:
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self.submodules.timer0 = timer.Timer()
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def add_cpu_or_bridge(self, cpu_or_bridge):
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if self.finalized:
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raise FinalizeError
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if hasattr(self, "cpu_or_bridge"):
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raise NotImplementedError("More than one CPU is not supported")
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self.submodules.cpu_or_bridge = cpu_or_bridge
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if with_timer:
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self.submodules.timer0 = timer.Timer()
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def initialize_rom(self, data):
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self.rom.mem.init = data
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@ -174,32 +164,29 @@ class SoCCore(Module):
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def do_finalize(self):
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registered_mems = {regions[0] for regions in self._memory_regions}
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if self.cpu_type != "none":
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for mem in "rom", "sram":
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if mem not in registered_mems:
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raise FinalizeError("CPU needs a {} to be registered with SoC.register_mem()".format(mem))
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for mem in "rom", "sram":
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if mem not in registered_mems:
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raise FinalizeError("CPU needs a {} to be registered with register_mem()".format(mem))
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# Wishbone
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self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters,
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self._wb_slaves, register=True)
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# CSR
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if self.with_csr:
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self.submodules.csrbankarray = csr_bus.CSRBankArray(self,
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lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override],
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data_width=self.csr_data_width, address_width=self.csr_address_width)
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self.submodules.csrcon = csr_bus.Interconnect(
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self.wishbone2csr.csr, self.csrbankarray.get_buses())
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for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
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self.add_csr_region(name, (self.mem_map["csr"] + 0x800*mapaddr) | self.shadow_base, self.csr_data_width, csrs)
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for name, memory, mapaddr, mmap in self.csrbankarray.srams:
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self.add_csr_region(name + "_" + memory.name_override, (self.mem_map["csr"] + 0x800*mapaddr) | self.shadow_base, self.csr_data_width, memory)
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self.submodules.csrbankarray = csr_bus.CSRBankArray(self,
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lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override],
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data_width=self.csr_data_width, address_width=self.csr_address_width)
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self.submodules.csrcon = csr_bus.Interconnect(
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self.wishbone2csr.csr, self.csrbankarray.get_buses())
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for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
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self.add_csr_region(name, (self.mem_map["csr"] + 0x800*mapaddr) | self.shadow_base, self.csr_data_width, csrs)
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for name, memory, mapaddr, mmap in self.csrbankarray.srams:
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self.add_csr_region(name + "_" + memory.name_override, (self.mem_map["csr"] + 0x800*mapaddr) | self.shadow_base, self.csr_data_width, memory)
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# Interrupts
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if hasattr(self.cpu_or_bridge, "interrupt"):
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for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)):
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if hasattr(self, k):
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self.comb += self.cpu_or_bridge.interrupt[v].eq(getattr(self, k).ev.irq)
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for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)):
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if hasattr(self, k):
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self.comb += self.cpu.interrupt[v].eq(getattr(self, k).ev.irq)
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def build(self, *args, **kwargs):
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self.platform.build(self, *args, **kwargs)
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