liteeth/phy/mii: simplify LiteEthPHYMIITX using Converter
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commit
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@ -139,6 +139,7 @@ def _remove_from_layout(layout, *args):
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if not remove:
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if not remove:
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r.append(f)
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r.append(f)
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return r
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return r
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def eth_phy_description(dw):
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def eth_phy_description(dw):
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payload_layout = [
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payload_layout = [
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("data", dw),
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("data", dw),
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@ -1,43 +1,28 @@
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from misoclib.com.liteeth.common import *
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from misoclib.com.liteeth.common import *
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from misoclib.com.liteeth.generic import *
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from misoclib.com.liteeth.generic import *
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def converter_description(dw):
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payload_layout = [("data", dw)]
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return EndpointDescription(payload_layout, packetized=True)
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class LiteEthPHYMIITX(Module):
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class LiteEthPHYMIITX(Module):
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def __init__(self, pads):
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def __init__(self, pads):
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self.sink = sink = Sink(eth_phy_description(8))
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self.sink = sink = Sink(eth_phy_description(8))
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###
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###
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if hasattr(pads, "tx_er"):
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if hasattr(pads, "tx_er"):
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self.sync += pads.tx_er.eq(0)
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self.sync += pads.tx_er.eq(0)
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tx_en_r = Signal()
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converter = Converter(converter_description(8), converter_description(4))
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tx_data_r = Signal(4)
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self.submodules += converter
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self.sync += [
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self.comb += [
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pads.tx_en.eq(tx_en_r),
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converter.sink.stb.eq(sink.stb),
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pads.tx_data.eq(tx_data_r)
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converter.sink.data.eq(sink.data),
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sink.ack.eq(converter.sink.ack),
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converter.source.ack.eq(1)
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]
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self.sync += [
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pads.tx_en.eq(converter.source.stb),
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pads.tx_data.eq(converter.source.data)
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]
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]
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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sink.ack.eq(1),
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If(sink.stb & sink.sop,
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sink.ack.eq(0),
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NextState("SEND_LO")
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)
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)
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fsm.act("SEND_LO",
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tx_data_r.eq(sink.data[0:4]),
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tx_en_r.eq(1),
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NextState("SEND_HI")
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)
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fsm.act("SEND_HI",
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tx_data_r.eq(sink.data[4:8]),
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tx_en_r.eq(1),
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sink.ack.eq(1),
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If(sink.stb & sink.eop,
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NextState("IDLE")
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).Else(
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NextState("SEND_LO")
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)
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)
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class LiteEthPHYMIIRX(Module):
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class LiteEthPHYMIIRX(Module):
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def __init__(self, pads):
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def __init__(self, pads):
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