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Merge pull request #405 from sajattack/sifive-triple 

add riscv-sifive-elf triple
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enjoy-digital 2020-03-02 09:30:05 +01:00 committed by GitHub
parent f27225c2de 68c013d13f
commit ddb264f3fd
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GPG Key ID: 4AEE18F83AFDEB23
5 changed files with 5 additions and 5 deletions
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2
litex/soc/cores/cpu/blackparrot/core.py
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@ -48,7 +48,7 @@ class BlackParrotRV64(CPU):
name = "blackparrot" name = "blackparrot"
data_width = 64 data_width = 64
endianness = "little" endianness = "little"
gcc_triple = ("riscv64-unknown-elf", "riscv64-linux") gcc_triple = ("riscv64-unknown-elf", "riscv64-linux", "riscv-sifive-elf")
linker_output_format = "elf64-littleriscv" linker_output_format = "elf64-littleriscv"
io_regions = {0x30000000: 0x20000000} # origin, length io_regions = {0x30000000: 0x20000000} # origin, length

2
litex/soc/cores/cpu/minerva/core.py
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@ -18,7 +18,7 @@ class Minerva(CPU):
data_width = 32 data_width = 32
endianness = "little" endianness = "little"
gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed", gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
"riscv64-linux") "riscv64-linux", "riscv-sifive-elf")
linker_output_format = "elf32-littleriscv" linker_output_format = "elf32-littleriscv"
io_regions = {0x80000000: 0x80000000} # origin, length io_regions = {0x80000000: 0x80000000} # origin, length

2
litex/soc/cores/cpu/picorv32/core.py
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@ -35,7 +35,7 @@ class PicoRV32(CPU):
data_width = 32 data_width = 32
endianness = "little" endianness = "little"
gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed", gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
"riscv64-linux") "riscv64-linux", "riscv-sifive-elf")
linker_output_format = "elf32-littleriscv" linker_output_format = "elf32-littleriscv"
io_regions = {0x80000000: 0x80000000} # origin, length io_regions = {0x80000000: 0x80000000} # origin, length

2
litex/soc/cores/cpu/rocket/core.py
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@ -67,7 +67,7 @@ class RocketRV64(CPU):
name = "rocket" name = "rocket"
data_width = 64 data_width = 64
endianness = "little" endianness = "little"
gcc_triple = ("riscv64-unknown-elf", "riscv64-linux") gcc_triple = ("riscv64-unknown-elf", "riscv64-linux", "riscv-sifive-elf")
linker_output_format = "elf64-littleriscv" linker_output_format = "elf64-littleriscv"
io_regions = {0x10000000: 0x70000000} # origin, length io_regions = {0x10000000: 0x70000000} # origin, length

2
litex/soc/cores/cpu/vexriscv/core.py
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@ -79,7 +79,7 @@ class VexRiscv(CPU, AutoCSR):
data_width = 32 data_width = 32
endianness = "little" endianness = "little"
gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed", gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
"riscv64-linux") "riscv64-linux", "riscv-sifive-elf")
linker_output_format = "elf32-littleriscv" linker_output_format = "elf32-littleriscv"
io_regions = {0x80000000: 0x80000000} # origin, length io_regions = {0x80000000: 0x80000000} # origin, length