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link: split SATALinkLayer in SATALinkLayerTX and SATALinkLayerRX
This commit is contained in:
Florent Kermarrec
parent
d3974882e4
commit
ddd4b65f44
2 changed files with 136 additions and 103 deletions
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@ -7,159 +7,192 @@ from lib.sata.link.scrambler import SATAScrambler
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from lib.sata.link.cont import SATACONTInserter, SATACONTRemover
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# TODO:
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# - Test D2H
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# - Do more tests
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class SATALinkLayer(Module):
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from_rx = [
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("idle", 1),
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("insert", 32),
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("det", 32)
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]
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class SATALinkLayerTX(Module):
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def __init__(self, phy):
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self.sink = Sink(link_layout(32))
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self.source = Source(link_layout(32))
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self.from_rx = Sink(from_rx)
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###
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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# TX
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# insert CRC
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tx_crc = SATACRCInserter(link_layout(32))
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self.submodules += tx_crc
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crc = SATACRCInserter(link_layout(32))
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self.submodules += crc
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# scramble
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tx_scrambler = SATAScrambler(link_layout(32))
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self.submodules += tx_scrambler
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scrambler = SATAScrambler(link_layout(32))
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self.submodules += scrambler
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# graph
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# connect CRC / scrambler
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self.comb += [
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Record.connect(self.sink, tx_crc.sink),
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Record.connect(tx_crc.source, tx_scrambler.sink)
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Record.connect(self.sink, crc.sink),
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Record.connect(crc.source, scrambler.sink)
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]
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# inserter CONT and scrambled data between
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# CONT and next primitive
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tx_cont = SATACONTInserter(phy_layout(32))
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self.submodules += tx_cont
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cont = SATACONTInserter(phy_layout(32))
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self.submodules += cont
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# datas / primitives mux
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tx_insert = Signal(32)
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insert = Signal(32)
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self.comb += [
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If(tx_insert != 0,
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tx_cont.sink.stb.eq(1),
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tx_cont.sink.data.eq(tx_insert),
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tx_cont.sink.charisk.eq(0x0001),
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).Elif(fsm.ongoing("H2D_COPY"),
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tx_cont.sink.stb.eq(tx_scrambler.source.stb),
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tx_cont.sink.data.eq(tx_scrambler.source.d),
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tx_scrambler.source.ack.eq(tx_cont.sink.ack),
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tx_cont.sink.charisk.eq(0)
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If(self.from_rx.insert,
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cont.sink.stb.eq(1),
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cont.sink.data.eq(self.from_rx.insert),
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cont.sink.charisk.eq(0x0001),
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).
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Elif(insert,
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cont.sink.stb.eq(1),
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cont.sink.data.eq(insert),
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cont.sink.charisk.eq(0x0001),
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).Elif(fsm.ongoing("COPY"),
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cont.sink.stb.eq(scrambler.source.stb),
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cont.sink.data.eq(scrambler.source.d),
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scrambler.source.ack.eq(cont.sink.ack),
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cont.sink.charisk.eq(0)
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)
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]
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self.comb += Record.connect(cont.source, phy.sink)
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# graph
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self.comb += Record.connect(tx_cont.source, phy.sink)
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# FSM
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fsm.act("IDLE",
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insert.eq(primitives["SYNC"]),
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If(scrambler.source.stb & scrambler.source.sop,
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If(self.from_rx.idle,
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NextState("RDY")
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)
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)
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)
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fsm.act("RDY",
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insert.eq(primitives["X_RDY"]),
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If(self.from_rx.det == primitives["R_RDY"],
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NextState("SOF")
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)
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)
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fsm.act("SOF",
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insert.eq(primitives["SOF"]),
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If(phy.sink.ack,
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NextState("COPY")
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)
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)
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fsm.act("COPY",
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If(self.from_rx.det == primitives["HOLD"],
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insert.eq(primitives["HOLDA"]),
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).Elif(~scrambler.source.stb,
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insert.eq(primitives["HOLD"]),
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).Elif(scrambler.source.stb & scrambler.source.eop & scrambler.source.ack,
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NextState("EOF")
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)
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)
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fsm.act("EOF",
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insert.eq(primitives["EOF"]),
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If(phy.sink.ack,
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NextState("WTRM")
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)
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)
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fsm.act("WTRM",
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insert.eq(primitives["WTRM"]),
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If(self.from_rx.det == primitives["R_OK"],
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NextState("IDLE")
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).Elif(self.from_rx.det == primitives["R_ERR"],
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NextState("IDLE")
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)
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)
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# RX
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class SATALinkLayerRX(Module):
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def __init__(self, phy):
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self.source = Source(link_layout(32))
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self.to_tx = Source(from_rx)
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###
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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# CONT remover
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rx_cont = SATACONTRemover(phy_layout(32))
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self.submodules += rx_cont
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# graph
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self.comb += Record.connect(phy.source, rx_cont.sink)
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cont = SATACONTRemover(phy_layout(32))
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self.submodules += cont
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self.comb += Record.connect(phy.source, cont.sink)
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# datas / primitives detection
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rx_det = Signal(32)
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insert = Signal(32)
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det = Signal(32)
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self.comb += \
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If(rx_cont.source.stb & (rx_cont.source.charisk == 0b0001),
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rx_det.eq(rx_cont.source.data)
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If(cont.source.stb & (cont.source.charisk == 0b0001),
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det.eq(cont.source.data)
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)
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# descrambler
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rx_scrambler = SATAScrambler(link_layout(32))
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self.submodules += rx_scrambler
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scrambler = SATAScrambler(link_layout(32))
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self.submodules += scrambler
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# check CRC
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rx_crc = SATACRCChecker(link_layout(32))
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self.submodules += rx_crc
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crc = SATACRCChecker(link_layout(32))
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self.submodules += crc
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# graph
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self.comb += [
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If(fsm.ongoing("D2H_COPY") & (rx_det == 0),
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rx_scrambler.sink.stb.eq(rx_cont.source.stb & (rx_cont.source.charisk == 0)),
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rx_scrambler.sink.d.eq(rx_cont.source.data),
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If(fsm.ongoing("COPY") & (det == 0),
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scrambler.sink.stb.eq(cont.source.stb & (cont.source.charisk == 0)),
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scrambler.sink.d.eq(cont.source.data),
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),
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rx_cont.source.ack.eq(1),
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Record.connect(rx_scrambler.source, rx_crc.sink),
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Record.connect(rx_crc.source, self.source)
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cont.source.ack.eq(1),
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Record.connect(scrambler.source, crc.sink),
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Record.connect(crc.source, self.source)
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]
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# FSM
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# FSM
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fsm.act("IDLE",
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tx_insert.eq(primitives["SYNC"]),
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If(rx_det == primitives["X_RDY"],
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NextState("D2H_RDY")
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).Elif(tx_scrambler.source.stb & tx_scrambler.source.sop,
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NextState("H2D_RDY")
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If(det == primitives["X_RDY"],
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NextState("RDY")
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)
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)
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# Host to Device
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fsm.act("H2D_RDY",
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tx_insert.eq(primitives["X_RDY"]),
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If(rx_det == primitives["R_RDY"],
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NextState("H2D_SOF")
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fsm.act("RDY",
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insert.eq(primitives["R_RDY"]),
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If(det == primitives["SOF"],
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NextState("COPY")
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)
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)
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fsm.act("H2D_SOF",
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tx_insert.eq(primitives["SOF"]),
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If(phy.sink.ack,
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NextState("H2D_COPY")
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fsm.act("COPY",
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If(det == primitives["HOLD"],
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insert.eq(primitives["HOLDA"])
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).Elif(det == primitives["EOF"],
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NextState("WTRM")
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)
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)
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fsm.act("H2D_COPY",
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If(rx_det == primitives["HOLD"],
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tx_insert.eq(primitives["HOLDA"]),
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).Elif(~tx_scrambler.source.stb,
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tx_insert.eq(primitives["HOLD"]),
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).Elif(tx_scrambler.source.stb & tx_scrambler.source.eop & tx_scrambler.source.ack,
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NextState("H2D_EOF")
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fsm.act("EOF",
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If(det == primitives["WTRM"],
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NextState("WTRM")
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)
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)
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fsm.act("H2D_EOF",
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tx_insert.eq(primitives["EOF"]),
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If(phy.sink.ack,
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NextState("H2D_WTRM")
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)
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)
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fsm.act("H2D_WTRM",
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tx_insert.eq(primitives["WTRM"]),
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If(rx_det == primitives["R_OK"],
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NextState("IDLE")
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).Elif(rx_det == primitives["R_ERR"],
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fsm.act("WTRM",
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insert.eq(primitives["R_OK"]),
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If(det == primitives["SYNC"],
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NextState("IDLE")
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)
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)
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# Device to Host
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fsm.act("D2H_RDY",
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tx_insert.eq(primitives["R_RDY"]),
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If(rx_det == primitives["SOF"],
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NextState("D2H_COPY")
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)
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)
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fsm.act("D2H_COPY",
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If(rx_det == primitives["HOLD"],
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tx_insert.eq(primitives["HOLDA"])
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).Elif(rx_det == primitives["EOF"],
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NextState("D2H_WTRM")
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)
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)
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fsm.act("D2H_EOF",
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If(rx_det == primitives["WTRM"],
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NextState("D2H_WTRM")
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)
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)
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fsm.act("D2H_WTRM",
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tx_insert.eq(primitives["R_OK"]),
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If(rx_det == primitives["SYNC"],
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NextState("IDLE")
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)
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)
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# to TX
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self.comb += [
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self.to_tx.idle.eq(fsm.ongoing("IDLE")),
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self.to_tx.insert.eq(insert),
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self.to_tx.det.eq(det)
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]
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class SATALinkLayer(Module):
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def __init__(self, phy):
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self.submodules.tx = SATALinkLayerTX(phy)
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self.submodules.rx = SATALinkLayerRX(phy)
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self.comb += Record.connect(self.rx.to_tx, self.tx.from_rx)
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self.sink, self.source = self.tx.sink, self.rx.source
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