Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

integration/builder: avoid specific _generate_standalone_includes

This commit is contained in:
Florent Kermarrec 2019-09-23 09:26:47 +02:00
parent 735ea196dd
commit dde6dd027b
1 changed files with 36 additions and 55 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

91
litex/soc/integration/builder.py
View File

@ -77,39 +77,40 @@ class Builder:
generated_dir = os.path.join(buildinc_dir, "generated") generated_dir = os.path.join(buildinc_dir, "generated")
os.makedirs(generated_dir, exist_ok=True) os.makedirs(generated_dir, exist_ok=True)
variables_contents = [] if cpu_type is not None:
def define(k, v): variables_contents = []
variables_contents.append("{}={}\n".format(k, _makefile_escape(v))) def define(k, v):
for k, v in cpu_interface.get_cpu_mak(self.soc.cpu, self.compile_software): variables_contents.append("{}={}\n".format(k, _makefile_escape(v)))
define(k, v) for k, v in cpu_interface.get_cpu_mak(self.soc.cpu, self.compile_software):
# Distinguish between LiteX and MiSoC. define(k, v)
define("LITEX", "1") # Distinguish between LiteX and MiSoC.
# Distinguish between applications running from main RAM and define("LITEX", "1")
# flash for user-provided software packages. # Distinguish between applications running from main RAM and
exec_profiles = { # flash for user-provided software packages.
"COPY_TO_MAIN_RAM" : "0", exec_profiles = {
"EXECUTE_IN_PLACE" : "0" "COPY_TO_MAIN_RAM" : "0",
} "EXECUTE_IN_PLACE" : "0"
if "main_ram" in (m[0] for m in memory_regions): }
exec_profiles["COPY_TO_MAIN_RAM"] = "1" if "main_ram" in (m[0] for m in memory_regions):
else: exec_profiles["COPY_TO_MAIN_RAM"] = "1"
exec_profiles["EXECUTE_IN_PLACE"] = "1" else:
for k, v in exec_profiles.items(): exec_profiles["EXECUTE_IN_PLACE"] = "1"
define(k, v) for k, v in exec_profiles.items():
define("SOC_DIRECTORY", soc_directory) define(k, v)
variables_contents.append("export BUILDINC_DIRECTORY\n") define("SOC_DIRECTORY", soc_directory)
define("BUILDINC_DIRECTORY", buildinc_dir) variables_contents.append("export BUILDINC_DIRECTORY\n")
for name, src_dir in self.software_packages: define("BUILDINC_DIRECTORY", buildinc_dir)
define(name.upper() + "_DIRECTORY", src_dir) for name, src_dir in self.software_packages:
write_to_file( define(name.upper() + "_DIRECTORY", src_dir)
os.path.join(generated_dir, "variables.mak"), write_to_file(
"".join(variables_contents)) os.path.join(generated_dir, "variables.mak"),
write_to_file( "".join(variables_contents))
os.path.join(generated_dir, "output_format.ld"), write_to_file(
cpu_interface.get_linker_output_format(self.soc.cpu)) os.path.join(generated_dir, "output_format.ld"),
write_to_file( cpu_interface.get_linker_output_format(self.soc.cpu))
os.path.join(generated_dir, "regions.ld"), write_to_file(
cpu_interface.get_linker_regions(memory_regions)) os.path.join(generated_dir, "regions.ld"),
cpu_interface.get_linker_regions(memory_regions))
write_to_file( write_to_file(
os.path.join(generated_dir, "mem.h"), os.path.join(generated_dir, "mem.h"),
cpu_interface.get_mem_header(memory_regions, flash_boot_address, shadow_base)) cpu_interface.get_mem_header(memory_regions, flash_boot_address, shadow_base))
@ -129,24 +130,6 @@ class Builder:
self.soc.sdram.controller.settings.phy, self.soc.sdram.controller.settings.phy,
self.soc.sdram.controller.settings.timing)) self.soc.sdram.controller.settings.timing))
def _generate_standalone_includes(self):
buildinc_dir = os.path.join(self.output_dir, "software", "include")
generated_dir = os.path.join(buildinc_dir, "generated")
csr_regions = self.soc.get_csr_regions()
constants = self.soc.get_constants()
os.makedirs(generated_dir, exist_ok=True)
write_to_file(
os.path.join(generated_dir, "csr.h"),
cpu_interface.get_csr_header(csr_regions, constants))
if isinstance(self.soc, soc_sdram.SoCSDRAM):
if hasattr(self.soc, "sdram"):
write_to_file(
os.path.join(generated_dir, "sdram_phy.h"),
get_sdram_phy_c_header(
self.soc.sdram.controller.settings.phy,
self.soc.sdram.controller.settings.timing))
def _generate_csr_map(self, csr_json=None, csr_csv=None): def _generate_csr_map(self, csr_json=None, csr_csv=None):
memory_regions = self.soc.get_memory_regions() memory_regions = self.soc.get_memory_regions()
csr_regions = self.soc.get_csr_regions() csr_regions = self.soc.get_csr_regions()
@ -195,11 +178,9 @@ class Builder:
os.makedirs(self.output_dir, exist_ok=True) os.makedirs(self.output_dir, exist_ok=True)
if self.soc.cpu_type is None: self._generate_includes()
self._generate_standalone_includes() if self.soc.cpu_type is not None:
else:
self._prepare_software() self._prepare_software()
self._generate_includes()
self._generate_software(not self.soc.integrated_rom_initialized) self._generate_software(not self.soc.integrated_rom_initialized)
if self.soc.integrated_rom_size and self.compile_software: if self.soc.integrated_rom_size and self.compile_software:
if not self.soc.integrated_rom_initialized: if not self.soc.integrated_rom_initialized: