integration/builder: avoid specific _generate_standalone_includes
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735ea196dd
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dde6dd027b
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@ -77,6 +77,7 @@ class Builder:
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generated_dir = os.path.join(buildinc_dir, "generated")
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os.makedirs(generated_dir, exist_ok=True)
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if cpu_type is not None:
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variables_contents = []
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def define(k, v):
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variables_contents.append("{}={}\n".format(k, _makefile_escape(v)))
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@ -129,24 +130,6 @@ class Builder:
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self.soc.sdram.controller.settings.phy,
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self.soc.sdram.controller.settings.timing))
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def _generate_standalone_includes(self):
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buildinc_dir = os.path.join(self.output_dir, "software", "include")
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generated_dir = os.path.join(buildinc_dir, "generated")
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csr_regions = self.soc.get_csr_regions()
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constants = self.soc.get_constants()
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os.makedirs(generated_dir, exist_ok=True)
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write_to_file(
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os.path.join(generated_dir, "csr.h"),
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cpu_interface.get_csr_header(csr_regions, constants))
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if isinstance(self.soc, soc_sdram.SoCSDRAM):
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if hasattr(self.soc, "sdram"):
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write_to_file(
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os.path.join(generated_dir, "sdram_phy.h"),
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get_sdram_phy_c_header(
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self.soc.sdram.controller.settings.phy,
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self.soc.sdram.controller.settings.timing))
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def _generate_csr_map(self, csr_json=None, csr_csv=None):
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memory_regions = self.soc.get_memory_regions()
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csr_regions = self.soc.get_csr_regions()
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@ -195,11 +178,9 @@ class Builder:
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os.makedirs(self.output_dir, exist_ok=True)
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if self.soc.cpu_type is None:
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self._generate_standalone_includes()
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else:
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self._prepare_software()
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self._generate_includes()
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if self.soc.cpu_type is not None:
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self._prepare_software()
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self._generate_software(not self.soc.integrated_rom_initialized)
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if self.soc.integrated_rom_size and self.compile_software:
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if not self.soc.integrated_rom_initialized:
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