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test: mac_wishbone_tb OK

This commit is contained in:
Florent Kermarrec 2015-01-28 21:54:09 +01:00
parent 44113d754f
commit ddf0579644
2 changed files with 54 additions and 28 deletions
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6
liteeth/mac/__init__.py
View File

@ -10,7 +10,11 @@ class LiteEthMAC(Module, AutoCSR):
if interface == "core": if interface == "core":
self.sink, self.source = self.core.sink, self.core.source self.sink, self.source = self.core.sink, self.core.source
elif interface == "wishbone": elif interface == "wishbone":
self.interface = wishbone.LiteEthMACWishboneInterface(dw, 2, 2) self.submodules.interface = wishbone.LiteEthMACWishboneInterface(dw, 2, 2)
self.comb += [
Record.connect(self.interface.source, self.core.sink),
Record.connect(self.core.source, self.interface.sink)
]
self.ev, self.bus = self.interface.sram.ev, self.interface.bus self.ev, self.bus = self.interface.sram.ev, self.interface.bus
self.csrs = self.interface.get_csrs() self.csrs = self.interface.get_csrs()
elif interface == "dma": elif interface == "dma":

38
liteeth/test/mac_wishbone_tb.py
View File

@ -3,10 +3,11 @@ from migen.bus import wishbone
from migen.bus.transactions import * from migen.bus.transactions import *
from migen.sim.generic import run_simulation from migen.sim.generic import run_simulation
from misoclib.ethmac import EthMAC from liteeth.common import *
from misoclib.ethmac.phy import loopback from liteeth.mac import LiteEthMAC
from misoclib.ethmac.test.common import * from liteeth.test.common import *
from liteeth.test.model import phy, mac
class WishboneMaster: class WishboneMaster:
def __init__(self, obj): def __init__(self, obj):
@ -62,10 +63,25 @@ class SRAMReaderDriver:
self.obj.ev.done.clear = 0 self.obj.ev.done.clear = 0
yield yield
class SRAMWriterDriver:
def __init__(self, obj):
self.obj = obj
def wait_available(self):
while self.obj.ev.available.pending == 0:
yield
def clear_available(self):
self.obj.ev.available.clear = 1
yield
self.obj.ev.available.clear = 0
yield
class TB(Module): class TB(Module):
def __init__(self): def __init__(self):
self.submodules.ethphy = loopback.LoopbackPHY() self.submodules.phy_model = phy.PHY(8, debug=False)
self.submodules.ethmac = EthMAC(phy=self.ethphy, with_hw_preamble_crc=True) self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=True)
self.submodules.ethmac = LiteEthMAC(phy=self.phy_model, dw=32, interface="wishbone", with_hw_preamble_crc=True)
# use sys_clk for each clock_domain # use sys_clk for each clock_domain
self.clock_domains.cd_eth_rx = ClockDomain() self.clock_domains.cd_eth_rx = ClockDomain()
@ -85,17 +101,19 @@ class TB(Module):
selfp.cd_eth_tx.rst = 0 selfp.cd_eth_tx.rst = 0
wishbone_master = WishboneMaster(selfp.ethmac.bus) wishbone_master = WishboneMaster(selfp.ethmac.bus)
sram_reader_driver = SRAMReaderDriver(selfp.ethmac.sram_reader) sram_reader_driver = SRAMReaderDriver(selfp.ethmac.interface.sram.reader)
sram_writer_driver = SRAMWriterDriver(selfp.ethmac.interface.sram.writer)
sram_writer_slots_offset = [0x000, 0x200] sram_writer_slots_offset = [0x000, 0x200]
sram_reader_slots_offset = [0x400, 0x600] sram_reader_slots_offset = [0x400, 0x600]
length = 1500+2 length = 150+2
tx_payload = [seed_to_data(i, True) % 0xFF for i in range(length)] + [0, 0, 0, 0] tx_payload = [seed_to_data(i, True) % 0xFF for i in range(length)] + [0, 0, 0, 0]
errors = 0 errors = 0
while True:
for slot in range(2): for slot in range(2):
print("slot {}:".format(slot)) print("slot {}:".format(slot))
# fill tx memory # fill tx memory
@ -108,6 +126,10 @@ class TB(Module):
yield from sram_reader_driver.wait_done() yield from sram_reader_driver.wait_done()
yield from sram_reader_driver.clear_done() yield from sram_reader_driver.clear_done()
# wait rx
yield from sram_writer_driver.wait_available()
yield from sram_writer_driver.clear_available()
# get rx payload (loopback on PHY Model) # get rx payload (loopback on PHY Model)
rx_payload = [] rx_payload = []
for i in range(length//4+1): for i in range(length//4+1):
@ -120,4 +142,4 @@ class TB(Module):
print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e)) print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
if __name__ == "__main__": if __name__ == "__main__":
run_simulation(TB(), vcd_name="my.vcd") run_simulation(TB(), ncycles=3000, vcd_name="my.vcd", keep_files=True)