soc/cores/cpu/urv: Add DataBusToWishbone and use it.
This commit is contained in:
Florent Kermarrec
parent
2b3913982c
commit
de9d3ab314
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@ -65,6 +65,70 @@ class InstructionBusToWishbone(LiteXModule):
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)
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)
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# uRV Data Bus To Wishbone -------------------------------------------------------------------------
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data_bus_layout = [
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("addr", 32),
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("data_s", 32),
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("data_l", 32),
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("sel", 4),
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("store", 1),
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("load", 1),
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("load_done", 1),
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("store_done", 1)
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]
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class DataBusToWishbone(LiteXModule):
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def __init__(self, dbus, wb_dbus):
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self.fifo = fifo = stream.SyncFIFO(
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layout=[("addr", 32), ("we", 1), ("data", 32), ("sel", 4)],
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depth=16,
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)
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self.comb += [
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fifo.sink.valid.eq(dbus.store | dbus.load),
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fifo.sink.we.eq(dbus.store),
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fifo.sink.addr.eq(dbus.addr),
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fifo.sink.data.eq(dbus.data_s),
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fifo.sink.sel.eq(dbus.sel),
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]
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self.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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If(fifo.source.valid,
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If(fifo.source.we,
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NextState("WRITE")
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).Else(
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NextState("READ")
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)
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)
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)
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fsm.act("WRITE",
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wb_dbus.stb.eq(1),
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wb_dbus.cyc.eq(1),
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wb_dbus.we.eq(1),
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wb_dbus.adr.eq(fifo.source.addr),
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wb_dbus.sel.eq(fifo.source.sel),
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wb_dbus.dat_w.eq(fifo.source.data),
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If(wb_dbus.ack,
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fifo.source.ready.eq(1),
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dbus.store_done.eq(1),
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NextState("IDLE")
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)
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)
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fsm.act("READ",
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wb_dbus.stb.eq(1),
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wb_dbus.cyc.eq(1),
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wb_dbus.we.eq(0),
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wb_dbus.adr.eq(fifo.source.addr),
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wb_dbus.sel.eq(fifo.source.sel),
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If(wb_dbus.ack,
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fifo.source.ready.eq(1),
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dbus.load_done.eq(1),
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dbus.data_l.eq(wb_dbus.dat_r),
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NextState("IDLE")
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)
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)
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# uRV ----------------------------------------------------------------------------------------------
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class uRV(CPU):
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@ -97,18 +161,10 @@ class uRV(CPU):
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self.periph_buses = [ibus, dbus] # Peripheral buses (Connected to main SoC's bus).
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self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM).
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# uRV Signals.
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# ------------
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# uRV Buses.
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# ----------
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im_bus = Record(instruction_bus_layout)
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dm_addr = Signal(32)
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dm_data_s = Signal(32)
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dm_data_l = Signal(32)
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dm_data_select = Signal(4)
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dm_store = Signal()
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dm_load = Signal()
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dm_load_done = Signal()
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dm_store_done = Signal()
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dm_bus = Record(data_bus_layout)
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# uRV Instance.
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# -------------
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@ -134,70 +190,21 @@ class uRV(CPU):
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i_im_valid_i = im_bus.valid,
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# Data Mem Bus.
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o_dm_addr_o = dm_addr,
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o_dm_data_s_o = dm_data_s,
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i_dm_data_l_i = dm_data_l,
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o_dm_data_select_o = dm_data_select,
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o_dm_addr_o = dm_bus.addr,
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o_dm_data_s_o = dm_bus.data_s,
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i_dm_data_l_i = dm_bus.data_l,
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o_dm_data_select_o = dm_bus.sel,
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o_dm_store_o = dm_store,
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o_dm_load_o = dm_load,
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i_dm_load_done_i = dm_load_done,
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i_dm_store_done_i = dm_store_done,
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o_dm_store_o = dm_bus.store,
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o_dm_load_o = dm_bus.load,
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i_dm_load_done_i = dm_bus.load_done,
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i_dm_store_done_i = dm_bus.store_done,
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)
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# uRV Bus Adaptation.
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# -------------------
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self.submodules += InstructionBusToWishbone(im_bus, ibus)
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# uRV Data Bus.
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# -------------
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self.dm_fifo = dm_fifo = stream.SyncFIFO(
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layout = [("addr", 32), ("we", 1), ("data", 32), ("sel", 4)],
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depth = 16,
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)
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self.comb += [
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dm_fifo.sink.valid.eq(dm_store | dm_load),
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dm_fifo.sink.we.eq(dm_store),
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dm_fifo.sink.addr.eq(dm_addr),
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dm_fifo.sink.data.eq(dm_data_s),
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dm_fifo.sink.sel.eq(dm_data_select),
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]
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self.dm_fsm = dm_fsm = FSM(reset_state="IDLE")
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dm_fsm.act("IDLE",
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If(dm_fifo.source.valid,
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If(dm_fifo.source.we,
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NextState("WRITE")
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).Else(
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NextState("READ")
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)
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)
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)
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dm_fsm.act("WRITE",
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dbus.stb.eq(1),
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dbus.cyc.eq(1),
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dbus.we.eq(1),
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dbus.adr.eq(dm_fifo.source.addr),
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dbus.sel.eq(dm_fifo.source.sel),
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dbus.dat_w.eq(dm_fifo.source.data),
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If(dbus.ack,
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dm_fifo.source.ready.eq(1),
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dm_store_done.eq(1),
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NextState("IDLE")
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)
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)
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dm_fsm.act("READ",
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dbus.stb.eq(1),
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dbus.cyc.eq(1),
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dbus.we.eq(0),
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dbus.adr.eq(dm_fifo.source.addr),
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dbus.sel.eq(dm_fifo.source.sel),
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If(dbus.ack,
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dm_fifo.source.ready.eq(1),
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dm_load_done.eq(1),
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dm_data_l.eq(dbus.dat_r),
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NextState("IDLE")
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)
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)
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self.submodules += DataBusToWishbone(dm_bus, dbus)
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# Add Verilog sources.
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# --------------------
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