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vhd2v: Use GHDL directly 

As of April 2022, GHDL can output Verilog directly without the use of
yosys. This simplifies the build environment for flows that simply want
to convert VHDL to Verilog.

Note that this removes some arguments from ghdl that are not required to
synthesise ether Microwatt or neorv32.

Signed-off-by: Joel Stanley <joel@jms.id.au>
This commit is contained in:
Joel Stanley 2022-10-28 10:21:53 +10:30
parent e3c33191b0
commit deafbf5efe
1 changed files with 16 additions and 16 deletions
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32
litex/build/vhd2v_converter.py
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@ -62,10 +62,10 @@ class VHD2VConverter(Module):
self._force_convert = force_convert self._force_convert = force_convert
self._add_instance = add_instance self._add_instance = add_instance
self._ghdl_opts = "--ieee=synopsys -fexplicit -frelaxed-rules --std=08 " self._ghdl_opts = ["--std=08", "--no-formal"]
if work_package is not None: if work_package is not None:
self._ghdl_opts += f"--work={self._work_package} " self._ghdl_opts.append(f"--work={self._work_package}")
self._ghdl_opts += "\\"
def add_source(self, filename): def add_source(self, filename):
""" """
@ -116,28 +116,28 @@ class VHD2VConverter(Module):
inst_name += f"_{len(v_list)}" inst_name += f"_{len(v_list)}"
verilog_out = os.path.join(self._build_dir, f"{inst_name}.v") verilog_out = os.path.join(self._build_dir, f"{inst_name}.v")
script = os.path.join(self._build_dir, f"{inst_name}.ys")
ys = []
ys.append("ghdl " + self._ghdl_opts)
ip_params = dict() ip_params = dict()
generics = [] generics = []
for k, v in self._params.items(): for k, v in self._params.items():
if k.startswith("p_"): if k.startswith("p_"):
ys.append("-g" + k[2:] + "=" + str(v) + " \\") generics.append("-g" + k[2:] + "=" + str(v))
else: else:
ip_params[k] = v ip_params[k] = v
from litex.build import tools cmd = ["ghdl", "--synth", "--out=verilog"]
cmd += self._ghdl_opts
cmd += generics
cmd += self._sources
cmd += ["-e", self._top_entity]
import subprocess import subprocess
for source in self._sources: from litex.build import tools
ys.append(source + " \\")
ys.append(f"-e {self._top_entity}") with open(verilog_out, 'w') as output:
ys.append("chformal -assert -remove") s = subprocess.run(cmd, stdout=output)
ys.append("write_verilog {}".format(verilog_out)) if s.returncode:
tools.write_to_file(script, "\n".join(ys)) raise OSError(f"Unable to convert {inst_name} to verilog, please check your GHDL install")
if subprocess.call(["yosys", "-q", "-m", "ghdl", script]):
raise OSError(f"Unable to convert {inst_name} to verilog, please check your GHDL-Yosys-plugin install")
# more than one instance of this core? rename top entity to avoid conflict # more than one instance of this core? rename top entity to avoid conflict
if inst_name != self._top_entity: if inst_name != self._top_entity: