cpu/naxriscv: Minor cleanups on recent changes.

litex/soc/cores/cpu/naxriscv/core.py

@@ -398,7 +398,7 @@ class NaxRiscv(CPU):
             o_peripheral_clint_rresp   = clintbus.r.resp,
         )
         soc.bus.add_slave("clint", clintbus, region=soc_region_cls(origin=soc.mem_map.get("clint"), size=0x1_0000, cached=False))
-        self.soc = soc # Save SoC instance to retrieve the final mem layout on finalization
+        self.soc = soc # FIXME: Save SoC instance to retrieve the final mem layout on finalization.
 
     def add_memory_buses(self, address_width, data_width):
         nax_data_width = 64

litex/soc/cores/cpu/vexriscv_smp/core.py

@@ -445,7 +445,7 @@ class VexRiscvSMP(CPU):
         )
         soc.bus.add_slave("clint", clintbus, region=soc_region_cls(origin=soc.mem_map.get("clint"), size=0x1_0000, cached=False))
 
-    def add_memory_buses(self, address_width, data_width, accessible_region):
+    def add_memory_buses(self, address_width, data_width):
         VexRiscvSMP.litedram_width = data_width
 
         from litedram.common import LiteDRAMNativePort

litex/soc/integration/soc.py

@@ -1475,16 +1475,17 @@ class LiteXSoC(SoC):
             sdram_size = min(sdram_size, size)
 
         # Add SDRAM region.
-        main_ram_region = SoCRegion(origin=self.mem_map.get("main_ram", origin), 
-                                    size=sdram_size,
-                                    mode="rwx")
+        main_ram_region = SoCRegion(
+            origin = self.mem_map.get("main_ram", origin),
+            size   = sdram_size,
+            mode   = "rwx")
         self.bus.add_region("main_ram", main_ram_region)
 
         # Add CPU's direct memory buses (if not already declared) ----------------------------------
         if hasattr(self.cpu, "add_memory_buses"):
             self.cpu.add_memory_buses(
-                address_width      = 32,
-                data_width         = sdram.crossbar.controller.data_width
+                address_width = 32,
+                data_width    = sdram.crossbar.controller.data_width
             )
 
         # Connect CPU's direct memory buses to LiteDRAM --------------------------------------------