platforms/kc705: add ddram_dual_rank
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@ -140,6 +140,41 @@ _io = [
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Misc("VCCAUX_IO=HIGH")
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),
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("ddram_dual_rank", 0,
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Subsignal("a", Pins(
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"AH12 AG13 AG12 AF12 AJ12 AJ13 AJ14 AH14",
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"AK13 AK14 AF13 AE13 AJ11 AH11 AK10 AK11"),
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IOStandard("SSTL15")),
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Subsignal("ba", Pins("AH9 AG9 AK9"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("AD9"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("AC11"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("AE9"), IOStandard("SSTL15")),
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Subsignal("cs_n", Pins("AC12 AE8"), IOStandard("SSTL15")),
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Subsignal("dm", Pins("Y16 AB17 AF17 AE16 AK5 AJ3 AF6 AC7"),
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IOStandard("SSTL15")),
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Subsignal("dq", Pins(
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"AA15 AA16 AC14 AD14 AA17 AB15 AE15 Y15",
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"AB19 AD16 AC19 AD17 AA18 AB18 AE18 AD18",
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"AG19 AK19 AG18 AF18 AH19 AJ19 AE19 AD19",
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"AK16 AJ17 AG15 AF15 AH17 AG14 AH15 AK15",
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"AK8 AK6 AG7 AF7 AF8 AK4 AJ8 AJ6",
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"AH5 AH6 AJ2 AH2 AH4 AJ4 AK1 AJ1",
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"AF1 AF2 AE4 AE3 AF3 AF5 AE1 AE5",
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"AC1 AD3 AC4 AC5 AE6 AD6 AC2 AD4"),
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IOStandard("SSTL15_T_DCI")),
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Subsignal("dqs_p", Pins("AC16 Y19 AJ18 AH16 AH7 AG2 AG4 AD2"),
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IOStandard("DIFF_SSTL15")),
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Subsignal("dqs_n", Pins("AC15 Y18 AK18 AJ16 AJ7 AH1 AG3 AD1"),
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IOStandard("DIFF_SSTL15")),
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Subsignal("clk_p", Pins("AG10 AE11"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("AH10 AF11"), IOStandard("DIFF_SSTL15")),
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Subsignal("cke", Pins("AF10 AE10"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("AD8 AC10"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("AK3"), IOStandard("LVCMOS15")),
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Misc("SLEW=FAST"),
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Misc("VCCAUX_IO=HIGH")
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),
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("eth_clocks", 0,
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Subsignal("tx", Pins("M28")),
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Subsignal("gtx", Pins("K30")),
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