efinix: supports for EfinixTristateImpl with nbits > 1
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@ -65,24 +65,36 @@ class EfinixAsyncResetSynchronizer:
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class EfinixTristateImpl(Module):
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def __init__(self, platform, io, o, oe, i=None):
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nbits, sign = value_bits_sign(io)
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assert nbits == 1
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io_name = platform.get_pin_name(io)
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io_loc = platform.get_pin_location(io)
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io_o = platform.add_iface_io(io_name + "_OUT")
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io_oe = platform.add_iface_io(io_name + "_OE")
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io_i = platform.add_iface_io(io_name + "_IN")
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self.comb += io_o.eq(o)
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self.comb += io_oe.eq(oe)
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if i is not None:
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self.comb += i.eq(io_i)
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block = {
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"type" : "GPIO",
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"mode" : "INOUT",
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"name" : io_name,
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"location" : [io_loc[0]],
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}
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platform.toolchain.ifacewriter.blocks.append(block)
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platform.toolchain.excluded_ios.append(io_name)
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for bit in range(nbits):
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io_name = platform.get_pin_name(io[bit])
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io_loc = platform.get_pin_location(io[bit])
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io_o = platform.add_iface_io(io_name + "_OUT")
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io_oe = platform.add_iface_io(io_name + "_OE")
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io_i = platform.add_iface_io(io_name + "_IN")
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self.comb += io_o.eq(o[bit])
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self.comb += io_oe.eq(oe)
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if i[bit] is not None:
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self.comb += i[bit].eq(io_i)
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block = {
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"type" : "GPIO",
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"mode" : "INOUT",
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"name" : io_name,
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"location" : [io_loc[0]],
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}
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platform.toolchain.ifacewriter.blocks.append(block)
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# Remove the group from the io list
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exclude = platform.get_pin_name(io[0], without_index=True)
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# In case of a single signal, there is still a '0' index
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# to be remove at the end
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if (nbits == 1) and (exclude[:-1] == '0'):
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exclude = exclude[:-1]
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platform.toolchain.excluded_ios.append(exclude)
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class EfinixTristate(Module):
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@staticmethod
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@ -100,7 +100,10 @@ class EfinixPlatform(GenericPlatform):
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for s, pins, others, resource in sc:
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if s == sig:
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if resource[2]:
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return resource[0] + "_" + resource[2] + (f"{idx}" if slc else "")
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name = resource[0] + "_" + resource[2]
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if without_index is False:
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name = name + (f"{idx}" if slc else "")
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return name
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else:
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return resource[0] + (f"{idx}" if slc else "")
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return None
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