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soc_sdram: update with litedram

This commit is contained in:
Florent Kermarrec 2018-09-09 02:10:50 +02:00
parent bebc667da6
commit df3f003ecd
1 changed files with 6 additions and 2 deletions
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8
litex/soc/integration/soc_sdram.py
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@ -15,8 +15,12 @@ __all__ = ["SoCSDRAM", "soc_sdram_args", "soc_sdram_argdict"]
class ControllerInjector(Module, AutoCSR):
def __init__(self, phy, geom_settings, timing_settings, **kwargs):
self.submodules.dfii = dfii.DFIInjector(geom_settings.addressbits, geom_settings.bankbits,
phy.settings.dfi_databits, phy.settings.nphases)
self.submodules.dfii = dfii.DFIInjector(
geom_settings.addressbits,
geom_settings.bankbits,
phy.settings.nranks,
phy.settings.dfi_databits,
phy.settings.nphases)
self.comb += self.dfii.master.connect(phy.dfi)
self.submodules.controller = controller = core.LiteDRAMController(