tools/litex_json2dts: switch VexRiscv to SMP, update SDCard dts.
This commit is contained in:
Florent Kermarrec
parent
0a9c9562dc
commit
df92e2aea7
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@ -34,6 +34,15 @@ def generate_dts(d):
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# Boot Arguments -----------------------------------------------------------------------------------
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linux_initrd_start_offset = {
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"mor1kx": 8*mB,
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"vexriscv smp-linux" : 16*mB,
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}
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linux_initrd_end_offset = {
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"mor1kx": 16*mB,
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"vexriscv smp-linux" : 24*mB,
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}
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dts += """
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chosen {{
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bootargs = "mem={main_ram_size_mb}M@0x{main_ram_base:x} rootwait console=liteuart earlycon=sbi root=/dev/ram0 init=/sbin/init swiotlb=32";
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@ -43,41 +52,40 @@ def generate_dts(d):
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""".format(main_ram_base=d["memories"]["main_ram"]["base"],
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main_ram_size=d["memories"]["main_ram"]["size"],
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main_ram_size_mb=d["memories"]["main_ram"]["size"] // mB,
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linux_initrd_start=d["memories"]["main_ram"]["base"] + 8*mB,
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linux_initrd_end=d["memories"]["main_ram"]["base"] + 16*mB)
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linux_initrd_start=d["memories"]["main_ram"]["base"] + linux_initrd_start_offset[cpu_name],
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linux_initrd_end=d["memories"]["main_ram"]["base"] + linux_initrd_end_offset[cpu_name])
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# CPU ----------------------------------------------------------------------------------------------
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if cpu_name == "vexriscv_linux":
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if cpu_name == "vexriscv smp-linux":
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dts += """
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cpus {{
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <{sys_clk_freq}>;
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""".format(sys_clk_freq=int(50e6) if "sim" in d["constants"] else d["constants"]["config_clock_frequency"])
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cpus = range(int(d["constants"]["config_cpu_count"]))
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for cpu in cpus:
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dts += """
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cpu@{cpu} {{
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device_type = "cpu";
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compatible = "riscv";
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riscv,isa = "rv32ima";
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mmu-type = "riscv,sv32";
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reg = <0>;
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status = "okay";
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L{irq}: interrupt-controller {{
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#interrupt-cells = <0x00000001>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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}};
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}};
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""".format(cpu=cpu, irq=cpu)
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dts += """
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cpus {{
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <{sys_clk_freq}>;
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cpu@0 {{
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clock-frequency = <{sys_clk_freq}>;
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compatible = "spinalhdl,vexriscv", "sifive,rocket0", "riscv";
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d-cache-block-size = <0x40>;
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d-cache-sets = <0x40>;
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d-cache-size = <0x8000>;
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d-tlb-sets = <0x1>;
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d-tlb-size = <0x20>;
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device_type = "cpu";
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i-cache-block-size = <0x40>;
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i-cache-sets = <0x40>;
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i-cache-size = <0x8000>;
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i-tlb-sets = <0x1>;
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i-tlb-size = <0x20>;
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mmu-type = "riscv,sv32";
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reg = <0x0>;
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riscv,isa = "rv32ima";
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sifive,itim = <0x1>;
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status = "okay";
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tlb-split;
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}};
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}};
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""".format(sys_clk_freq=int(50e6) if "sim" in d["constants"] else d["constants"]["config_clock_frequency"])
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};
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"""
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elif cpu_name == "mor1kx":
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@ -93,11 +101,6 @@ def generate_dts(d):
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}};
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""".format(sys_clk_freq=d["constants"]["config_clock_frequency"])
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else:
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raise Exception("ERROR: unsupported CPU type {}".format(cpu_name))
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# Memory -------------------------------------------------------------------------------------------
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dts += """
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@ -108,19 +111,19 @@ def generate_dts(d):
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""".format(main_ram_base=d["memories"]["main_ram"]["base"],
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main_ram_size=d["memories"]["main_ram"]["size"])
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if "emulator" in d["memories"]:
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if "opensbi" in d["memories"]:
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dts += """
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reserved-memory {{
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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vexriscv_emulator@{emulator_base:x} {{
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reg = <0x{emulator_base:x} 0x{emulator_size:x}>;
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opensbi@{opensbi_base:x} {{
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reg = <0x{opensbi_base:x} 0x{opensbi_size:x}>;
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}};
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}};
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""".format(emulator_base=d["memories"]["emulator"]["base"],
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emulator_size=d["memories"]["emulator"]["size"])
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""".format(opensbi_base=d["memories"]["opensbi"]["base"],
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opensbi_size=d["memories"]["opensbi"]["size"])
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# SoC ----------------------------------------------------------------------------------------------
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@ -135,21 +138,33 @@ def generate_dts(d):
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# Interrupt controller -----------------------------------------------------------------------------
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if cpu_name == "vexriscv_linux":
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irq_controller_compatible = "vexriscv,intc0"
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if cpu_name == "vexriscv smp-linux":
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dts += """
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plic: interrupt-controller@{plic_base:x} {{
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compatible = "sifive,plic-1.0.0", "sifive,fu540-c000-plic";
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reg = <0x{plic_base:x} 0x400000>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupts-extended = <
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{cpu_mapping}>;
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riscv,ndev = <32>;
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}};
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""".format( plic_base=d["memories"]["plic"]["base"],
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cpu_mapping="\n\t\t\t\t".join(["&L{} 11 &L{} 9".format(cpu, cpu) for cpu in cpus]))
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elif cpu_name == "mor1kx":
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irq_controller_compatible = "opencores,or1k-pic"
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dts += """
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intc0: interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <1>;
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compatible = "opencores,or1k-pic";
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status = "okay";
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};
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"""
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else:
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raise Exception("Unsupported CPU type: {}".format(cpu_name))
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dts += """
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intc0: interrupt-controller {{
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interrupt-controller;
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#interrupt-cells = <1>;
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compatible = "{compatible}";
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status = "okay";
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}};
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""".format(compatible=irq_controller_compatible)
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# SoC Controller -----------------------------------------------------------------------------------
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@ -486,21 +501,23 @@ def generate_dts(d):
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# SDCARD -------------------------------------------------------------------------------------------
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if "sdcore" in d["csr_bases"]:
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dts += """
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mmc0: mmc@{mmc_csr_base:x} {{
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compatible = "litex,mmc";
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bus-width = <4>;
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reg = <
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0x{sdphy_csr_base:x} 0x100
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0x{sdcore_csr_base:x} 0x100
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>;
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status = "okay";
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}};
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""".format(mmc_csr_base=d["csr_bases"]["sdcore"],
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sdphy_csr_base=d["csr_bases"]["sdphy"],
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sdcore_csr_base=d["csr_bases"]["sdcore"])
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dts += """
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mmc0: mmc@{mmc_csr_base:x} {{
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compatible = "litex,mmc";
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reg = <
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0x{sdphy_csr_base:x} 0x100
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0x{sdcore_csr_base:x} 0x100
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0x{sdblock2mem:x} 0x100
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0x{sdmem2block:x} 0x100>;
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bus-width = <0x04>;
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status = "okay";
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}};
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""".format(mmc_csr_base=d["csr_bases"]["sdcore"],
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sdphy_csr_base=d["csr_bases"]["sdphy"],
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sdcore_csr_base=d["csr_bases"]["sdcore"],
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sdblock2mem=d["csr_bases"]["sdblock2mem"],
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sdmem2block=d["csr_bases"]["sdmem2block"]
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)
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dts += """
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};
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"""
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