add modelsim simulation and start fixing init
This commit is contained in:
Florent Kermarrec
parent
1d053bd7ee
commit
dfbec91a62
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@ -13,6 +13,12 @@ class K7SATAPHY(Module):
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self.source = Source([("d", 32)], True)
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gtx = K7SATAPHYGTX(pads, "SATA3")
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self.comb += [
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#gtx.rxrate.eq(0b001),
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#gtx.txrate.eq(0b001),
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gtx.rxrate.eq(0b0),
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gtx.txrate.eq(0b0),
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]
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clocking = K7SATAPHYClocking(pads, gtx)
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rxalign = K7SATAPHYRXAlign()
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rxconvert = K7SATAPHYRXConvert()
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@ -34,10 +34,13 @@ class K7SATAPHYClocking(Module):
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# TX clocking
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refclk = Signal()
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self.specials += Instance("IBUFDS_GTE2",
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i_CEB=0,
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i_I=pads.refclk_p,
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i_IB=pads.refclk_n,
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o_O=refclk
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)
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self.comb += gtx.gtrefclk0.eq(refclk)
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mmcm_reset = Signal()
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mmcm_locked = Signal()
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mmcm_drp = DRPBus()
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@ -52,10 +55,10 @@ class K7SATAPHYClocking(Module):
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# DRP
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i_DCLK=mmcm_drp.clk, i_DEN=mmcm_drp.en, o_DRDY=mmcm_drp.rdy, i_DWE=mmcm_drp.we,
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i_DADDR=mmcm_drp.addr, i_DI=mmcm_drp.di, i_DO=mmcm_drp.do,
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i_DADDR=mmcm_drp.addr, i_DI=mmcm_drp.di, o_DO=mmcm_drp.do,
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# VCO
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0,
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=6.666,
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p_CLKFBOUT_MULT_F=8.000, p_CLKFBOUT_PHASE=0.000, p_DIVCLK_DIVIDE=2,
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i_CLKIN1=mmcm_clk_i, i_CLKFBIN=mmcm_fb, o_CLKFBOUT=mmcm_fb,
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@ -63,7 +66,7 @@ class K7SATAPHYClocking(Module):
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p_CLKOUT0_DIVIDE_F=4.000, p_CLKOUT0_PHASE=0.000, o_CLKOUT0=mmcm_clk0_o,
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# CLK1
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p_CLKOUT1_DIVIDE_F=8.000, p_CLKOUT1_PHASE=0.000, o_CLKOUT1=mmcm_clk1_o,
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p_CLKOUT1_DIVIDE=8, p_CLKOUT1_PHASE=0.000, o_CLKOUT1=mmcm_clk1_o,
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),
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Instance("BUFG", i_I=mmcm_clk0_o, o_O=self.cd_sata_tx.clk),
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Instance("BUFG", i_I=mmcm_clk1_o, o_O=self.cd_sata.clk),
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@ -130,16 +133,25 @@ class K7SATAPHYClocking(Module):
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)
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# Reset
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# initial reset generation
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rst_cnt = Signal(8)
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rst_cnt_done = Signal()
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self.sync += \
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If(~rst_cnt_done,
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rst_cnt.eq(rst_cnt+1)
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)
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self.comb += rst_cnt_done.eq(rst_cnt==255)
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self.comb += [
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# GTXE2
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gtx.rxuserrdy.eq(gtx.cplllock),
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gtx.txuserrdy.eq(gtx.cplllock),
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# TX
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gtx.gttxreset.eq(self.reset | self.transceiver_reset | ~gtx.cplllock),
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gtx.gttxreset.eq(rst_cnt_done & (self.reset | self.transceiver_reset | ~gtx.cplllock)),
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# RX
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gtx.gtrxreset.eq(self.reset | self.transceiver_reset | ~gtx.cplllock),
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gtx.gtrxreset.eq(rst_cnt_done & (self.reset | self.transceiver_reset | ~gtx.cplllock)),
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# PLL
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gtx.cpllreset.eq(self.reset)
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gtx.cpllreset.eq(rst_cnt_done & self.reset)
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]
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# SATA TX/RX clock domains
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self.specials += [
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@ -157,7 +157,7 @@ class K7SATAPHYHostCtrl(Module):
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self.sync.sata += \
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If(fsm.ongoing("SEND_ALIGN"),
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If(self.rxdata[7:0] == K28_5,
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If(self.rxdata[0:8] == K28_5,
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non_align_cnt.eq(non_align_cnt + 1)
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).Else(
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non_align_cnt.eq(0)
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@ -82,6 +82,8 @@ class K7SATAPHYGTX(Module):
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# Transmit Ports - TX Data Path interface
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self.gttxreset = Signal()
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self.txpcsreset = Signal()
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self.txpmareset = Signal()
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self.txdata = Signal()
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self.txoutclk = Signal()
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self.txoutclkfabric = Signal()
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@ -93,7 +95,7 @@ class K7SATAPHYGTX(Module):
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self.txresetdone = Signal()
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# Transmit Ports - TX Ports for PCI Express
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self.txelecidle = Signal()
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self.txelecidle = Signal(reset=1)
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# Transmit Ports - TX Ports for SATA
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self.txcomfinish = Signal()
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@ -128,7 +130,7 @@ class K7SATAPHYGTX(Module):
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"p_SIM_TX_EIDLE_DRIVE_LEVEL":"X",
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"p_SIM_RESET_SPEEDUP":"TRUE",
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"p_SIM_CPLLREFCLK_SEL":0b001,
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"p_SIM_VERSION":"4.0",
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"p_SIM_VERSION":"3.0",
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# RX Byte and Word Alignment Attributes
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"p_ALIGN_COMMA_DOUBLE":"FALSE",
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@ -138,9 +140,9 @@ class K7SATAPHYGTX(Module):
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"p_ALIGN_MCOMMA_VALUE":K28_5,
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"p_ALIGN_PCOMMA_DET":"TRUE",
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"p_ALIGN_PCOMMA_VALUE":~K28_5,
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"p_SHOW_REALIGN_COMMA":"FALSE",
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"p_SHOW_REALIGN_COMMA":"TRUE",
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"p_RXSLIDE_AUTO_WAIT":7,
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"p_RXSLIDE_MODE":"OFF",
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"p_RXSLIDE_MODE":"PCS",
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"p_RX_SIG_VALID_DLY":10,
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# RX 8B/10B Decoder Attributes
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@ -303,7 +305,7 @@ class K7SATAPHYGTX(Module):
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# TX Buffer Attributes
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"p_TXBUF_EN":"FALSE",
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"p_TXBUF_RESET_ON_RATE_CHANGE":"FALSE",
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"p_TXBUF_RESET_ON_RATE_CHANGE":"TRUE",
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"p_TXDLY_CFG":0x1f,
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"p_TXDLY_LCFG":0x030,
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"p_TXDLY_TAP_CFG":0,
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@ -429,7 +431,7 @@ class K7SATAPHYGTX(Module):
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i_DRPADDR=self.drp.addr,
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i_DRPCLK=self.drp.clk,
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i_DRPDI=self.drp.di,
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i_DRPDO=self.drp.do,
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o_DRPDO=self.drp.do,
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i_DRPEN=self.drp.en,
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o_DRPRDY=self.drp.rdy,
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i_DRPWE=self.drp.we,
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@ -490,7 +492,7 @@ class K7SATAPHYGTX(Module):
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i_RXUSRCLK2=self.rxusrclk2,
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# Receive Ports - FPGA RX interface Ports
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i_RXDATA=self.rxdata,
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o_RXDATA=self.rxdata,
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# Receive Ports - Pattern Checker Ports
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#o_RXPRBSERR=,
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@ -505,7 +507,7 @@ class K7SATAPHYGTX(Module):
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i_RXDFEXYDOVRDEN=0,
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# Receive Ports - RX 8B/10B Decoder Ports
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i_RXDISPERR=self.rxdisperr,
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o_RXDISPERR=self.rxdisperr,
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o_RXNOTINTABLE=self.rxnotintable,
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# Receive Ports - RX AFE
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@ -730,8 +732,8 @@ class K7SATAPHYGTX(Module):
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i_TXSTARTSEQ=0,
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# Transmit Ports - TX Initialization and Reset Ports
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i_TXPCSRESET=0,
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i_TXPMARESET=0,
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i_TXPCSRESET=self.txpcsreset,
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i_TXPMARESET=self.txpmareset,
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o_TXRESETDONE=self.txresetdone,
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# Transmit Ports - TX OOB signalling Ports
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@ -820,8 +822,8 @@ class K7SATAPHYRXConvert(Module):
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# rearrange data
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self.comb += [
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self.source.stb.eq(self.rx_fifo.source.stb),
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self.source.payload.data.eq(Cat(rx_fifo.source.raw[0:32], rx_fifo.source.raw[36:36+32])),
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self.source.payload.charisk.eq(Cat(rx_fifo.source.raw[32:36], rx_fifo.source.raw[36+32:36+36])),
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self.source.payload.data.eq(Cat(rx_fifo.source.raw[0:16], rx_fifo.source.raw[18:18+16])),
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self.source.payload.charisk.eq(Cat(rx_fifo.source.raw[16:18], rx_fifo.source.raw[18+16:18+18])),
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self.rx_fifo.source.ack.eq(self.source.ack),
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]
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@ -0,0 +1,11 @@
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##############################################################################
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#
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# Compilation of SoC RTL files
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#
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##############################################################################
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set HDL_WORK "work"
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hdl_compile -v 2005 {
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../../misoc/build/testdesign-kc705_impact.v
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}
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@ -0,0 +1,8 @@
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##############################################################################
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#
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# Compilation of MiSoC TB files
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#
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##############################################################################
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hdl_compile -sim glbl.v
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hdl_compile -sim top_tb.v
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@ -0,0 +1,66 @@
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// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.15 2011/08/25 22:54:30 fphillip Exp $
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`timescale 1 ps / 1 ps
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module glbl ();
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parameter ROC_WIDTH = 100000;
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parameter TOC_WIDTH = 0;
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//-------- STARTUP Globals --------------
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wire GSR;
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wire GTS;
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wire GWE;
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wire PRLD;
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tri1 p_up_tmp;
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tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
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wire PROGB_GLBL;
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wire CCLKO_GLBL;
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reg GSR_int;
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reg GTS_int;
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reg PRLD_int;
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//-------- JTAG Globals --------------
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wire JTAG_TDO_GLBL;
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wire JTAG_TCK_GLBL;
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wire JTAG_TDI_GLBL;
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wire JTAG_TMS_GLBL;
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wire JTAG_TRST_GLBL;
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reg JTAG_CAPTURE_GLBL;
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reg JTAG_RESET_GLBL;
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reg JTAG_SHIFT_GLBL;
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reg JTAG_UPDATE_GLBL;
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reg JTAG_RUNTEST_GLBL;
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reg JTAG_SEL1_GLBL = 0;
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reg JTAG_SEL2_GLBL = 0 ;
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reg JTAG_SEL3_GLBL = 0;
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reg JTAG_SEL4_GLBL = 0;
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reg JTAG_USER_TDO1_GLBL = 1'bz;
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reg JTAG_USER_TDO2_GLBL = 1'bz;
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reg JTAG_USER_TDO3_GLBL = 1'bz;
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reg JTAG_USER_TDO4_GLBL = 1'bz;
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assign (weak1, weak0) GSR = GSR_int;
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assign (weak1, weak0) GTS = GTS_int;
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assign (weak1, weak0) PRLD = PRLD_int;
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initial begin
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GSR_int = 1'b1;
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PRLD_int = 1'b1;
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#(ROC_WIDTH)
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GSR_int = 1'b0;
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PRLD_int = 1'b0;
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end
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initial begin
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GTS_int = 1'b1;
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#(TOC_WIDTH)
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GTS_int = 1'b0;
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end
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endmodule
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@ -0,0 +1,29 @@
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set HDL_TOOLTYPE SIMULATION
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set HDL_TOOLNAME 0in
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set HDL_PUTS puts
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set HDL_MSG_FORMAT "********** %s **********"
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proc hdl_tool_library {lib} {
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}
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proc hdl_tool_compile {format version incdirs library define files behavioral} {
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set command analyze
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lappend command -work [string tolower $library]
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switch $format {
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"vhdl" {
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lappend command -vhdl
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}
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"verilog" {
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foreach d $define {
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lappend command +define+$d
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}
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foreach i $incdirs {
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lappend command +incdir+$i
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}
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}
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}
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foreach f $files {
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lappend command $f
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}
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puts [eval $command]
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}
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@ -0,0 +1,406 @@
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##############################################################################
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# Define some global variables
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##############################################################################
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if {![info exists HDL_LIBRARIES]} {
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set HDL_LIBRARIES ()
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}
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set HDL_TARGET "default_target"
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set HDL_PATH [pwd]
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set HDL_WORK "work"
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# Uncomment the following line to generate a log file for debug
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#set HDL_LOG [open "hdl_common.log" "w"]
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##############################################################################
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# Some utilities
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##############################################################################
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# Extract first element from a list (for argument processing)
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proc extract_first {list_name {option ""}} {
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upvar $list_name mylist
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if {[string length $option]>0 && [llength $mylist]==0} {
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error "Missing argument for option $option"
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}
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set first [lindex $mylist 0]
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if {[string length $option]>0 && [string match "-*" $first]} {
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error "Missing argument for option $option"
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}
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set mylist [lrange $mylist 1 end]
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return $first
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}
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# Clean-up file path
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proc clean_path {f} {
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# Add trailing /
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set f "$f/"
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# Remove double / (excepted leading)
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while {[regsub {(.)//} $f "\1/" f]} {}
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# Remove .
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while {[regsub {/\./} $f "/" f]} {}
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# Remove ..
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while {[regsub {/[^/.]+/\.\./} $f "/" f]} {}
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# Remove trailing /
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regsub {/$} $f "" f
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return $f
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}
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# Translate relative paths to absolute paths
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proc get_full_path {files} {
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global HDL_PATH
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set r {}
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# For DOS paths, replace \ by /
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regsub -all {\\} $files "/" files
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foreach f $files {
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hdl_debug " $f"
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# Append file path
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if {[string match "/*" $f] || [string match "?:/*" $f]} {
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# Path is an absolute path
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hdl_warning "Using absolute path $f"
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} else {
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# Path is a relative path
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set f [clean_path $HDL_PATH/$f]
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}
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hdl_debug " => $f"
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lappend r $f
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# Check access to file
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if {![file readable $f]} {
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error "Cannot read file $f"
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}
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}
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return $r
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}
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# Check if value match any pattern in the list
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proc match_list {mlist value} {
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set match 0
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foreach m $mlist {
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if [string match $m $value] {
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set match 1
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}
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}
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return $match
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}
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proc get_lib_path {} {
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if [file isdirectory "/cad/trash"] {
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set libs "/cad/trash[pwd]/libs"
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} elseif [file isdirectory "e:/trash"] {
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set libs [pwd]
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# Replace D:/ by D/ for local drive
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regsub ":" $libs "" libs
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# Remove leading // for network drive
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regsub "//" $libs "" libs
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set libs "e:/trash/$libs"
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} else {
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# No "trash" directory on this machine => work locally
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set libs "./libs"
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}
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file mkdir $libs
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return $libs
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}
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##############################################################################
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# Procedures to display messages
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##############################################################################
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# Write message to log file if logging enabled
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proc hdl_log { msg } {
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global HDL_LOG
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if [info exists HDL_LOG] {
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puts $HDL_LOG $msg
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flush $HDL_LOG
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}
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return
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}
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# Debug messages are sent only to log file
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proc hdl_debug { msg } {
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hdl_log "hdl_common - Debug: $msg"
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return
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}
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# According to the tool, "puts" or "echo" should be used
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# HDL_PUTS variable is used for this purpose
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# All message are also sent to log file
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proc hdl_puts { msg } {
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global HDL_PUTS
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$HDL_PUTS $msg
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hdl_log $msg
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return
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}
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proc hdl_note { msg } {
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hdl_puts "hdl_common - Note: $msg"
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return
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}
|
||||
|
||||
proc hdl_warning { msg } {
|
||||
hdl_puts "hdl_common - Warning: $msg"
|
||||
return
|
||||
}
|
||||
|
||||
proc hdl_message { args } {
|
||||
global HDL_MSG_FORMAT
|
||||
hdl_puts [format $HDL_MSG_FORMAT [join $args " "]]
|
||||
return
|
||||
}
|
||||
|
||||
##############################################################################
|
||||
# Procedures for compilation scripts
|
||||
##############################################################################
|
||||
|
||||
# Compile source files
|
||||
proc hdl_compile { args } {
|
||||
global HDL_TOOLTYPE HDL_TOOLNAME HDL_TARGET HDL_LIBRARIES HDL_WORK
|
||||
# Default values
|
||||
set format ""
|
||||
set version "93"
|
||||
set files {}
|
||||
set incdirs {}
|
||||
set only_for {}
|
||||
set not_for {}
|
||||
set toolname {}
|
||||
set tooltype "*"
|
||||
set library $HDL_WORK
|
||||
set define {}
|
||||
set behavioral 0
|
||||
|
||||
# Decode arguments
|
||||
while {[llength $args]} {
|
||||
set arg [extract_first args]
|
||||
switch -glob -- $arg {
|
||||
"-f" {
|
||||
set format [extract_first args "-f"]
|
||||
}
|
||||
"-v" {
|
||||
set version [extract_first args "-version"]
|
||||
}
|
||||
"-only_for" {
|
||||
set only_for [concat $only_for [extract_first args "-only_for"]]
|
||||
}
|
||||
"-not_for" {
|
||||
set not_for [concat $not_for [extract_first args "-not_for"]]
|
||||
}
|
||||
"-sim" {
|
||||
set tooltype "SIMULATION"
|
||||
set behavioral 1
|
||||
}
|
||||
"-syn" {
|
||||
set tooltype "SYNTHESIS"
|
||||
set behavioral 0
|
||||
}
|
||||
"-tool" {
|
||||
set toolname [concat $toolname [extract_first args "-tool"]]
|
||||
}
|
||||
"-incdir" {
|
||||
set incdirs [concat $incdirs [extract_first args "-incdir"]]
|
||||
}
|
||||
"-lib" {
|
||||
set library [extract_first args "-lib"]
|
||||
if {[string match "work" $library]} {
|
||||
hdl_warning "Specifying '-lib work' is useless"
|
||||
}
|
||||
}
|
||||
"-define" {
|
||||
set define [concat $define [extract_first args "-define"]]
|
||||
}
|
||||
"-*" {
|
||||
error "Unsupported argument $arg"
|
||||
}
|
||||
default {
|
||||
set files [concat $files $arg]
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
# Check arguments
|
||||
if {![llength $files]} {
|
||||
error "No file to compile"
|
||||
}
|
||||
# If no "-only_for" option given, use file for any target
|
||||
if {[llength $only_for]==0} {
|
||||
set only_for {*}
|
||||
}
|
||||
# If no "-tool" option given, use file for any tool
|
||||
if {[llength $toolname]==0} {
|
||||
set toolname {*}
|
||||
}
|
||||
|
||||
# Check if compilation is required
|
||||
if {[match_list $only_for $HDL_TARGET] && ![match_list $not_for $HDL_TARGET] &&
|
||||
[string match $tooltype $HDL_TOOLTYPE] && [match_list $toolname $HDL_TOOLNAME]} {
|
||||
# Create library if needed
|
||||
if {[lsearch -exact $HDL_LIBRARIES $library]<0} {
|
||||
hdl_note "Creating library $library"
|
||||
lappend HDL_LIBRARIES $library
|
||||
hdl_tool_library $library
|
||||
}
|
||||
# Compile files
|
||||
foreach f $files {
|
||||
# Warning if dummy file is used
|
||||
if {[string match "*dummy*" [string tolower $f]]} {
|
||||
hdl_note "Using [file tail $f]"
|
||||
}
|
||||
# Determine format
|
||||
if {![llength $format]} {
|
||||
if {[string match "*.vh?*" $f]} {
|
||||
set format "vhdl"
|
||||
} elseif {[string match "*.v*" $f]} {
|
||||
set format "verilog"
|
||||
set version "sv"
|
||||
} elseif {[string match "*.sv" $f]} {
|
||||
set format "verilog"
|
||||
set version "sv"
|
||||
}
|
||||
}
|
||||
}
|
||||
hdl_tool_compile $format $version [get_full_path $incdirs] $library $define [get_full_path $files] $behavioral
|
||||
}
|
||||
return
|
||||
}
|
||||
|
||||
# Change directory
|
||||
proc hdl_cd { path } {
|
||||
global HDL_PATH
|
||||
set HDL_PATH [get_full_path $path]
|
||||
hdl_debug "New path is $HDL_PATH"
|
||||
return
|
||||
}
|
||||
|
||||
# Execute script
|
||||
proc hdl_source { args } {
|
||||
global HDL_PATH HDL_TARGET HDL_WORK HDL_TOOLTYPE HDL_TOOLNAME
|
||||
# Save original values
|
||||
set save_path $HDL_PATH
|
||||
set save_target $HDL_TARGET
|
||||
set save_work $HDL_WORK
|
||||
# Default value
|
||||
set files {}
|
||||
set toolname {}
|
||||
set tooltype "*"
|
||||
set only_for {}
|
||||
set not_for {}
|
||||
# Process options
|
||||
while {[llength $args]} {
|
||||
set arg [extract_first args]
|
||||
switch -glob -- $arg {
|
||||
"-lib" {
|
||||
set HDL_WORK [extract_first args "-lib"]
|
||||
if {[string match "work" $HDL_WORK]} {
|
||||
hdl_warning "Specifying '-lib work' is useless"
|
||||
}
|
||||
}
|
||||
"-target" {
|
||||
set HDL_TARGET [extract_first args "-target"]
|
||||
}
|
||||
"-sim" {
|
||||
set tooltype "SIMULATION"
|
||||
set behavioral 1
|
||||
}
|
||||
"-syn" {
|
||||
set tooltype "SYNTHESIS"
|
||||
set behavioral 0
|
||||
}
|
||||
"-tool" {
|
||||
set toolname [concat $toolname [extract_first args "-tool"]]
|
||||
}
|
||||
"-only_for" {
|
||||
set only_for [concat $only_for [extract_first args "-only_for"]]
|
||||
}
|
||||
"-not_for" {
|
||||
set not_for [concat $not_for [extract_first args "-not_for"]]
|
||||
}
|
||||
"-*" {
|
||||
error "Unsupported argument $arg"
|
||||
}
|
||||
default {
|
||||
set files [concat $files $arg]
|
||||
}
|
||||
}
|
||||
}
|
||||
# Check arguments
|
||||
if {![llength $files]} {
|
||||
error "No script specified"
|
||||
}
|
||||
# If no "-only_for" option given, use file for any target
|
||||
if {[llength $only_for]==0} {
|
||||
set only_for {*}
|
||||
}
|
||||
# If no "-tool" option given, use file for any tool
|
||||
if {[llength $toolname]==0} {
|
||||
set toolname {*}
|
||||
}
|
||||
|
||||
# Check if compilation is required
|
||||
if {[match_list $only_for $HDL_TARGET] && ![match_list $not_for $HDL_TARGET] &&
|
||||
[string match $tooltype $HDL_TOOLTYPE] && [match_list $toolname $HDL_TOOLNAME]} {
|
||||
# Source scripts
|
||||
foreach script $files {
|
||||
# Change directory to script location
|
||||
hdl_cd [file dirname $script]
|
||||
# Execute script
|
||||
set script [get_full_path [file tail $script]]
|
||||
hdl_note "Source $script ($HDL_TARGET)"
|
||||
uplevel source $script
|
||||
# Restore original path
|
||||
set HDL_PATH $save_path
|
||||
hdl_debug "Back to directory $HDL_PATH"
|
||||
}
|
||||
}
|
||||
# Restore original values
|
||||
set HDL_TARGET $save_target
|
||||
set HDL_WORK $save_work
|
||||
#puts "Back to $HDL_PATH"
|
||||
return
|
||||
}
|
||||
|
||||
# Specify target
|
||||
proc hdl_set_target { args } {
|
||||
global HDL_TARGET env
|
||||
# Default values
|
||||
set use_env 0
|
||||
set default ""
|
||||
set target ""
|
||||
# Decode arguments
|
||||
while {[llength $args]} {
|
||||
set arg [extract_first args]
|
||||
switch -glob -- $arg {
|
||||
"-env" {
|
||||
set use_env 1
|
||||
}
|
||||
"-default" {
|
||||
set default [extract_first args "-default"]
|
||||
}
|
||||
"-*" {
|
||||
error "Unsupported argument $arg"
|
||||
}
|
||||
default {
|
||||
set target $arg
|
||||
}
|
||||
}
|
||||
}
|
||||
# Check arguments
|
||||
if {[llength $target]} {
|
||||
set HDL_TARGET $target
|
||||
hdl_note "Using target $HDL_TARGET"
|
||||
} elseif {$use_env} {
|
||||
if {[info exists env(HDL_TARGET)]} {
|
||||
set HDL_TARGET $env(HDL_TARGET)
|
||||
hdl_note "Using target $HDL_TARGET (from environment variable HDL_TARGET)"
|
||||
} elseif {[llength $default]} {
|
||||
set HDL_TARGET $default
|
||||
hdl_note "Using default target $HDL_TARGET (environment variable HDL_TARGET not defined)"
|
||||
} else {
|
||||
error "No environment variable defined and no default target"
|
||||
}
|
||||
} else {
|
||||
error "Missing argument"
|
||||
}
|
||||
return
|
||||
}
|
||||
|
||||
##############################################################################
|
||||
|
||||
# clock is an invalid command name for Synplify at least until version 2010.09
|
||||
# hdl_debug [clock format [clock seconds]]
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
set HDL_TOOLTYPE SYNTHESIS
|
||||
set HDL_TOOLNAME formality
|
||||
set HDL_PUTS puts
|
||||
set HDL_MSG_FORMAT "\n********** %s **********\n"
|
||||
|
||||
proc hdl_tool_library {lib} {
|
||||
define_design_lib $lib -path lib_$lib
|
||||
}
|
||||
|
||||
proc hdl_tool_compile {format version incdirs library define files behavioral} {
|
||||
global search_path
|
||||
if {[llength $define]} {
|
||||
error "-define not yet supported"
|
||||
}
|
||||
# Add include paths
|
||||
set search_path [concat $incdirs $search_path]
|
||||
# Compile files
|
||||
foreach f $files {
|
||||
if {[string match $format "vhdl"]} {
|
||||
if {[string match $version "93"]} {
|
||||
read_vhdl -93 -libname $library $f
|
||||
} else {
|
||||
read_vhdl -libname $library $f
|
||||
}
|
||||
} else {
|
||||
read_verilog -01 -libname $library $f
|
||||
}
|
||||
puts ""
|
||||
}
|
||||
# Remove include paths
|
||||
set search_path [lrange $search_path [llength $incdirs] end]
|
||||
}
|
||||
|
|
@ -0,0 +1,80 @@
|
|||
# Set the option CHECK_SYNTHESIS to 1 if you want to have -check_synthesis in simulation. For now
|
||||
# tools like Modelsim generate too many false positives so it is disabled by default:
|
||||
|
||||
set CHECK_SYNTHESIS 0
|
||||
|
||||
set NO_DEBUG 0
|
||||
|
||||
set HDL_TOOLTYPE SIMULATION
|
||||
set HDL_TOOLNAME modelsim
|
||||
set HDL_PUTS echo
|
||||
set HDL_MSG_FORMAT "********** %s **********"
|
||||
|
||||
# Return the directory containing library lib
|
||||
proc getvmap {lib} {
|
||||
if {[catch {vmap $lib} result]} {
|
||||
# Library does not exist yet => default directory
|
||||
return $lib
|
||||
}
|
||||
set dir ""
|
||||
# Get directory returned by vmap
|
||||
regexp { maps to directory (.*)\.$} $result match dir
|
||||
return $dir
|
||||
}
|
||||
|
||||
proc hdl_tool_library {lib} {
|
||||
set lib [string tolower $lib]
|
||||
# Delete library
|
||||
set path [getvmap $lib]
|
||||
if {[file isdirectory $path]} {
|
||||
catch {
|
||||
vdel -lib $path -all
|
||||
}
|
||||
}
|
||||
# Create library
|
||||
set path [get_lib_path]/$lib
|
||||
vlib $path
|
||||
vmap $lib $path
|
||||
}
|
||||
|
||||
proc hdl_tool_compile {format version incdirs library define files behavioral} {
|
||||
global CHECK_SYNTHESIS
|
||||
global NO_DEBUG
|
||||
switch $format {
|
||||
"vhdl" {
|
||||
set command vcom
|
||||
if { $version == 87 } {
|
||||
lappend command -87
|
||||
} elseif { $version == 93 } {
|
||||
lappend command -93
|
||||
}
|
||||
# More strict for synthesizable modules
|
||||
if { ! $behavioral && $CHECK_SYNTHESIS } {
|
||||
lappend command -check_synthesis
|
||||
}
|
||||
}
|
||||
"verilog" {
|
||||
set command vlog
|
||||
if {$version == "sv"} {
|
||||
lappend command -sv
|
||||
}
|
||||
lappend command -timescale "1ns/1ns"
|
||||
foreach d $define {
|
||||
lappend command +define+$d
|
||||
}
|
||||
foreach i $incdirs {
|
||||
lappend command +incdir+$i
|
||||
}
|
||||
}
|
||||
}
|
||||
if {$NO_DEBUG} {
|
||||
lappend command -nodebug
|
||||
}
|
||||
lappend command -work [string tolower $library]
|
||||
lappend command -quiet
|
||||
foreach f $files {
|
||||
lappend command $f
|
||||
}
|
||||
puts -nonewline [eval $command]
|
||||
return
|
||||
}
|
||||
|
|
@ -0,0 +1,91 @@
|
|||
set HDL_TOOLTYPE SIMULATION
|
||||
set HDL_TOOLNAME ncsim
|
||||
set HDL_PUTS puts
|
||||
set HDL_MSG_FORMAT "********** %s **********"
|
||||
|
||||
if {![file exists hdl.var]} {
|
||||
hdl_note "Creating default hdl.var"
|
||||
exec echo "DEFINE WORK work" > hdl.var
|
||||
}
|
||||
|
||||
if {![file exists cds.lib]} {
|
||||
hdl_note "Creating default cds.lib"
|
||||
exec echo "# This file was created automatically by hdl_ncsim.tcl" > cds.lib
|
||||
exec echo "# You can edit this file" >> cds.lib
|
||||
exec echo "# Please add the libraries that are not handled by hdl_ncsim.tcl" >> cds.lib
|
||||
exec echo "# (for example the Xilinx libraries compiled with compxlib)" >> cds.lib
|
||||
exec echo {INCLUDE ${CDS_INST_DIR}/tools/inca/files/cds.lib} >> cds.lib
|
||||
}
|
||||
|
||||
proc no_matching_line {pattern file} {
|
||||
return [catch {exec grep -q $pattern $file}]
|
||||
}
|
||||
|
||||
if {[no_matching_line "^INCLUDE mycds.lib$" cds.lib]} {
|
||||
hdl_note "Including mycds.lib in cds.lib"
|
||||
exec echo "INCLUDE mycds.lib" >> cds.lib
|
||||
}
|
||||
|
||||
hdl_note "Clean-up mycds.lib"
|
||||
exec echo "# This file is written automatically by hdl_ncsim.tcl" > mycds.lib
|
||||
exec echo "# Do not edit this file" >> mycds.lib
|
||||
exec echo "# It will be overwritten at each compilation" >> mycds.lib
|
||||
|
||||
proc hdl_tool_library {lib} {
|
||||
set lib [string tolower $lib]
|
||||
set path [get_lib_path]/${lib}_nc
|
||||
exec echo "DEFINE $lib $path" >> mycds.lib
|
||||
exec touch $path
|
||||
exec rm -r $path
|
||||
exec mkdir $path
|
||||
}
|
||||
|
||||
proc hdl_tool_compile {format version incdirs library define files behavioral} {
|
||||
switch $format {
|
||||
"vhdl" {
|
||||
set command "ncvhdl"
|
||||
if {$version != 87} {
|
||||
lappend command -v93
|
||||
}
|
||||
# Less strict VHDL for behavioral modules
|
||||
if {$behavioral} {
|
||||
lappend command -relax
|
||||
}
|
||||
}
|
||||
"verilog" {
|
||||
set command "ncvlog"
|
||||
if {$version == "sv"} {
|
||||
lappend command -sv
|
||||
}
|
||||
foreach d $define {
|
||||
lappend command -define $d
|
||||
}
|
||||
foreach i $incdirs {
|
||||
lappend command -incdir $i
|
||||
}
|
||||
}
|
||||
}
|
||||
lappend command -work [string tolower $library]
|
||||
lappend command -nocopyright
|
||||
foreach f $files {
|
||||
lappend command $f
|
||||
}
|
||||
eval $command
|
||||
}
|
||||
|
||||
# Allow launching NC-Sim tools directly in TCL
|
||||
proc ncvlog { args } {
|
||||
puts -nonewline [eval exec -keepnewline ncvlog $args]
|
||||
}
|
||||
proc ncvhdl { args } {
|
||||
puts -nonewline [eval exec -keepnewline ncvhdl $args]
|
||||
}
|
||||
proc ncelab { args } {
|
||||
puts -nonewline [eval exec -keepnewline ncelab $args]
|
||||
}
|
||||
proc ncsdfc { args } {
|
||||
puts -nonewline [eval exec -keepnewline ncsdfc $args]
|
||||
}
|
||||
proc ncsim { args } {
|
||||
puts -nonewline [eval exec -keepnewline ncsim $args]
|
||||
}
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
set HDL_TOOLTYPE SYNTHESIS
|
||||
set HDL_TOOLNAME QuartusII
|
||||
set HDL_PUTS puts
|
||||
set HDL_MSG_FORMAT "********** %s **********"
|
||||
|
||||
|
||||
proc hdl_tool_library {lib_list} {
|
||||
}
|
||||
|
||||
proc hdl_tool_compile {format version incdirs library define files behavioral} {
|
||||
#if {[llength $incdirs]} {
|
||||
# error "-incdir not yet supported"
|
||||
#}
|
||||
switch $format {
|
||||
"vhdl" {
|
||||
foreach f $files {
|
||||
set_global_assignment -name VHDL_FILE $f -library $library
|
||||
}
|
||||
}
|
||||
"verilog" {
|
||||
foreach d $define {
|
||||
set_global_assignment -name VERILOG_MACRO $d
|
||||
}
|
||||
foreach f $files {
|
||||
set_global_assignment -name VERILOG_FILE $f -library $library
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if { [catch { puts "Quartus hdl_common script" } ] } {
|
||||
# Disable puts for Quartus (doesn't work with the GUI since no stdout channel)
|
||||
proc hdl_puts { msg } {
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
set HDL_TOOLTYPE SYNTHESIS
|
||||
set HDL_TOOLNAME synopsys
|
||||
set HDL_PUTS puts
|
||||
set HDL_MSG_FORMAT "\n********** %s **********\n"
|
||||
|
||||
proc hdl_tool_library {lib_list} {
|
||||
foreach l $lib_list {
|
||||
set path [get_lib_path]/$l
|
||||
sh touch $path
|
||||
sh rm -r $path
|
||||
sh mkdir $path
|
||||
define_design_lib $l -path $path
|
||||
}
|
||||
}
|
||||
|
||||
proc hdl_tool_compile {format version incdirs library define files behavioral} {
|
||||
global search_path
|
||||
if {[llength $define]} {
|
||||
error "-define not yet supported"
|
||||
}
|
||||
# Add include paths
|
||||
set search_path [concat $incdirs $search_path]
|
||||
# Compile files
|
||||
foreach f $files {
|
||||
if {[string match $format "vhdl"]} {
|
||||
puts "Compiling source file $f"
|
||||
}
|
||||
analyze -format $format -work $library $f
|
||||
puts ""
|
||||
}
|
||||
# Remove include paths
|
||||
set search_path [lrange $search_path [llength $incdirs] end]
|
||||
}
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
set HDL_TOOLTYPE SYNTHESIS
|
||||
set HDL_TOOLNAME synplify
|
||||
set HDL_PUTS puts
|
||||
set HDL_MSG_FORMAT "********** %s **********"
|
||||
|
||||
proc hdl_tool_library {lib_list} {
|
||||
}
|
||||
|
||||
proc hdl_tool_compile {format version incdirs library define files behavioral} {
|
||||
if {[llength $define]} {
|
||||
error "-define not yet supported"
|
||||
}
|
||||
switch $format {
|
||||
"vhdl" {
|
||||
foreach f $files {
|
||||
add_file -vhdl -lib $library $f
|
||||
}
|
||||
}
|
||||
"verilog" {
|
||||
foreach i $incdirs {
|
||||
set_option -include_path "$i"
|
||||
}
|
||||
foreach f $files {
|
||||
add_file -verilog $f
|
||||
}
|
||||
}
|
||||
"ngc" {
|
||||
foreach i $incdirs {
|
||||
set_option -include_path "$i"
|
||||
}
|
||||
foreach f $files {
|
||||
add_file -xilinx $f
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
set HDL_TOOLTYPE SYNTHESIS
|
||||
set HDL_TOOLNAME XST
|
||||
set HDL_PUTS puts
|
||||
set HDL_MSG_FORMAT "********** %s **********"
|
||||
|
||||
proc hdl_tool_library {lib_list} {
|
||||
}
|
||||
|
||||
proc hdl_tool_compile {format version incdirs library define files behavioral} {
|
||||
global PROJECT_FILE
|
||||
|
||||
# do not use append, based on http://wiki.tcl.tk/1241
|
||||
set projectfile [open $PROJECT_FILE {WRONLY CREAT APPEND}]
|
||||
|
||||
if {[llength $define]} {
|
||||
error "-define not yet supported"
|
||||
}
|
||||
if {[llength $incdirs]} {
|
||||
error "-incdirs not yet supported"
|
||||
}
|
||||
puts "checking format"
|
||||
switch $format {
|
||||
"vhdl" {
|
||||
foreach f $files {
|
||||
puts $projectfile "vhdl $library $f"
|
||||
}
|
||||
}
|
||||
"verilog" {
|
||||
foreach f $files {
|
||||
puts $projectfile "verilog $library $f"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
close $projectfile
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
transcript on
|
||||
transcript file CustomTranscript
|
||||
|
||||
##############################################################################
|
||||
# Setup libraries
|
||||
vlib work
|
||||
vmap unisims_ver D:/Installs/Logiciels/Xilinx/ISE14.6/14.6/ISE_DS/ISE/verilog/mti_se/10.1c/nt/unisims_ver
|
||||
vmap secureip D:/Installs/Logiciels/Xilinx/ISE14.6/14.6/ISE_DS/ISE/verilog/mti_se/10.1c/nt/secureip
|
||||
|
||||
# Compile design
|
||||
##############################################################################
|
||||
|
||||
source hdl_common/hdl_common.tcl
|
||||
source hdl_common/hdl_modelsim.tcl
|
||||
|
||||
hdl_source compile_rtl.tcl
|
||||
hdl_source compile_tb.tcl
|
||||
|
||||
##############################################################################
|
||||
# Run simulation
|
||||
##############################################################################
|
||||
|
||||
vsim -t ps -L secureip -L unisims_ver -novopt glbl top_tb
|
||||
|
||||
set NumericStdNoWarnings 1
|
||||
set StdArithNoWarnings 1
|
||||
|
||||
log -r *
|
||||
do wave.do
|
||||
|
||||
onbreak {resume}
|
||||
run 2000us
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
`timescale 1ns/1ps
|
||||
|
||||
module top_tb();
|
||||
|
||||
reg refclk_p;
|
||||
wire refclk_n;
|
||||
initial refclk_p = 1'b1;
|
||||
always #3.33 refclk_p = ~refclk_p;
|
||||
assign refclk_n = ~refclk_p;
|
||||
|
||||
reg clk200_p;
|
||||
wire clk200_n;
|
||||
initial clk200_p = 1'b1;
|
||||
always #2.5 clk200_p = ~clk200_p;
|
||||
assign clk200_n = ~clk200_p;
|
||||
|
||||
wire sata_txp;
|
||||
wire sata_txn;
|
||||
wire sata_rxp;
|
||||
wire sata_rxn;
|
||||
|
||||
top dut(
|
||||
.serial_cts(1'b0),
|
||||
.serial_rts(1'b0),
|
||||
.serial_tx(),
|
||||
.serial_rx(1'b0),
|
||||
.clk200_p(clk200_p),
|
||||
.clk200_n(clk200_n),
|
||||
.sata_host_refclk_p(refclk_p),
|
||||
.sata_host_refclk_n(refclk_n),
|
||||
.sata_host_txp(sata_txp),
|
||||
.sata_host_txn(sata_txn),
|
||||
.sata_host_rxp(sata_rxp),
|
||||
.sata_host_rxn(sata_rxn),
|
||||
.sata_device_refclk_p(refclk_p),
|
||||
.sata_device_refclk_n(refclk_n),
|
||||
.sata_device_txp(sata_rxp),
|
||||
.sata_device_txn(sata_rxn),
|
||||
.sata_device_rxp(sata_txp),
|
||||
.sata_device_rxn(sata_txn)
|
||||
);
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue