software/libbase/isr.c: Simplify using __riscv_plic__ define.

litex/soc/cores/cpu/openc906/core.py

@@ -89,6 +89,7 @@ class OpenC906(CPU):
         flags =  "-mno-save-restore "
         flags += "-march=rv64gc -mabi=lp64d "
         flags += "-D__openc906__ "
+        flags += "-D__riscv_plic__ "
         flags += "-mcmodel=medany"
         return flags
 

litex/soc/cores/cpu/rocket/core.py

@@ -113,6 +113,7 @@ class Rocket(CPU):
         flags =  "-mno-save-restore "
         flags += f"-march={self.get_arch(self.variant)} -mabi=lp64 "
         flags += "-D__rocket__ "
+        flags += "-D__riscv_plic__ "
         flags += "-mcmodel=medany"
         return flags
 

litex/soc/cores/cpu/vexriscv_smp/core.py

@@ -169,6 +169,7 @@ class VexRiscvSMP(CPU):
     def gcc_flags(self):
         flags =  f" -march={VexRiscvSMP.get_arch()} -mabi={VexRiscvSMP.get_abi()}"
         flags += f" -D__vexriscv_smp__"
+        flags += f" -D__riscv_plic__"
         return flags
 
     # Reserved Interrupts.

litex/soc/software/libbase/isr.c

@@ -29,7 +29,7 @@ void isr(void)
     onetime++;
   }
 }
-#elif defined(__rocket__) || defined(__openc906__) || defined(__vexriscv_smp__)
+#elif defined(__riscv_plic__)
 
 // PLIC initialization.
 void plic_init(void);