test/test_targets: update and reorganize targets

This commit is contained in:
Florent Kermarrec 2018-09-24 01:15:33 +02:00
parent e9ed737037
commit e04530e0c4
1 changed files with 28 additions and 13 deletions

View File

@ -18,27 +18,42 @@ def build_test(socs):
class TestTargets(unittest.TestCase): class TestTargets(unittest.TestCase):
def test_arty(self): # altera boards
from litex.boards.targets.arty import BaseSoC, MiniSoC
errors = build_test([BaseSoC(), MiniSoC()])
self.assertEqual(errors, 0)
def test_de0nano(self): def test_de0nano(self):
from litex.boards.targets.de0nano import BaseSoC from litex.boards.targets.de0nano import BaseSoC
errors = build_test([BaseSoC()]) errors = build_test([BaseSoC()])
self.assertEqual(errors, 0) self.assertEqual(errors, 0)
def test_kc705(self): # xilinx boards
from litex.boards.targets.kc705 import BaseSoC, MiniSoC
errors = build_test([BaseSoC(), MiniSoC()])
self.assertEqual(errors, 0)
def test_minispartan6(self): def test_minispartan6(self):
from litex.boards.targets.minispartan6 import BaseSoC from litex.boards.targets.minispartan6 import BaseSoC
errors = build_test([BaseSoC()]) errors = build_test([BaseSoC()])
self.assertEqual(errors, 0) self.assertEqual(errors, 0)
def test_arty(self):
from litex.boards.targets.arty import BaseSoC, EthernetSoC
errors = build_test([BaseSoC(), EthernetSoC()])
self.assertEqual(errors, 0)
def test_nexys4ddr(self):
from litex.boards.targets.nexys4ddr import BaseSoC
errors = build_test([BaseSoC()])
self.assertEqual(errors, 0)
def test_nexys_video(self): def test_nexys_video(self):
from litex.boards.targets.nexys_video import BaseSoC, MiniSoC from litex.boards.targets.nexys_video import BaseSoC, EthernetSoC
errors = build_test([BaseSoC(), MiniSoC()]) errors = build_test([BaseSoC(), EthernetSoC()])
self.assertEqual(errors, 0) self.assertEqual(errors, 0)
def test_genesys2(self):
from litex.boards.targets.genesys2 import BaseSoC, EthernetSoC
errors = build_test([BaseSoC(), EthernetSoC()])
self.assertEqual(errors, 0)
def test_kc705(self):
from litex.boards.targets.kc705 import BaseSoC, EthernetSoC
errors = build_test([BaseSoC(), EthernetSoC()])
self.assertEqual(errors, 0)
# lattice boards