mibuild/lattice: use ODDRXD1 and new synthesis directive
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@ -1,6 +1,8 @@
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from migen.fhdl.std import *
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from migen.fhdl.std import *
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from migen.genlib.io import *
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from migen.genlib.io import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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class LatticeAsyncResetSynchronizerImpl(Module):
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class LatticeAsyncResetSynchronizerImpl(Module):
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def __init__(self, cd, async_reset):
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def __init__(self, cd, async_reset):
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rst1 = Signal()
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rst1 = Signal()
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@ -18,8 +20,9 @@ class LatticeAsyncResetSynchronizer:
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class LatticeDDROutputImpl(Module):
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class LatticeDDROutputImpl(Module):
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def __init__(self, i1, i2, o, clk):
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def __init__(self, i1, i2, o, clk):
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self.specials += Instance("ODDRA",
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self.specials += Instance("ODDRXD1",
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i_CLK=clk, i_RST=0,
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synthesis_directive="ODDRAPPS=\"SCLK_ALIGNED\"",
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i_SCLK=clk,
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i_DA=i1, i_DB=i2, o_Q=o,
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i_DA=i1, i_DB=i2, o_Q=o,
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)
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)
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