Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

sim: make sure replaced memory signals are always in VCD signal set

This commit is contained in:
Sebastien Bourdeauducq 2015-10-05 12:24:32 +08:00
parent 70e3280579
commit e0899c1424
1 changed files with 2 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
migen/sim/core.py
View File

@ -237,6 +237,8 @@ class Simulator:
signals.add(cd.clk) signals.add(cd.clk)
if cd.rst is not None: if cd.rst is not None:
signals.add(cd.rst) signals.add(cd.rst)
for memory_array in mta.replacements.values():
signals |= set(memory_array)
signals = sorted(signals, key=lambda x: x.duid) signals = sorted(signals, key=lambda x: x.duid)
self.vcd = VCDWriter(vcd_name, signals) self.vcd = VCDWriter(vcd_name, signals)