sim: make sure replaced memory signals are always in VCD signal set

2015-10-05 12:24:32 +08:00 · 2015-10-05 12:24:32 +08:00 · e0899c1424
parent 70e3280579
commit e0899c1424
1 changed files with 2 additions and 0 deletions
--- a/migen/sim/core.py
+++ b/migen/sim/core.py
@ -237,6 +237,8 @@ class Simulator:
                signals.add(cd.clk)
                if cd.rst is not None:
                    signals.add(cd.rst)
+            for memory_array in mta.replacements.values():
+                signals |= set(memory_array)
            signals = sorted(signals, key=lambda x: x.duid)
            self.vcd = VCDWriter(vcd_name, signals)