interconnect/wishbone: remove UpConverter (probably not used by anyone and would need to be rewritten).
We'll provide a better implementation if this is useful.
This commit is contained in:
Florent Kermarrec
parent
696b31ed18
commit
e0d2682055
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@ -15,8 +15,6 @@ from migen.genlib.fsm import FSM, NextState
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from litex.soc.interconnect import csr
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from litex.soc.interconnect import csr
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from litex.build.generic_platform import *
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from litex.build.generic_platform import *
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# TODO: rewrite without FlipFlop
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_layout = [
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_layout = [
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("adr", "adr_width", DIR_M_TO_S),
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("adr", "adr_width", DIR_M_TO_S),
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@ -322,178 +320,6 @@ class DownConverter(Module):
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cached_data.eq(master.dat_r)
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cached_data.eq(master.dat_r)
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)
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)
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@ResetInserter()
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@CEInserter()
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class FlipFlop(Module):
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def __init__(self, *args, **kwargs):
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self.d = Signal(*args, **kwargs)
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self.q = Signal(*args, **kwargs)
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self.sync += self.q.eq(self.d)
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class UpConverter(Module):
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"""UpConverter
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This module up-converts wishbone accesses and bursts from a master interface
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to a wider slave interface. This allows efficient use wishbone bursts.
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Writes:
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Wishbone writes are cached before being written to the slave. Access to
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the slave is done at the end of a burst or when address reach end of burst
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addressing.
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Reads:
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Cache is refilled only at the beginning of each burst, the subsequent
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reads of a burst use the cached data.
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"""
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def __init__(self, master, slave):
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dw_from = len(master.dat_r)
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dw_to = len(slave.dat_w)
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ratio = dw_to//dw_from
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ratiobits = log2_int(ratio)
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# # #
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write = Signal()
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evict = Signal()
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refill = Signal()
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read = Signal()
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address = FlipFlop(30)
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self.submodules += address
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self.comb += address.d.eq(master.adr)
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counter = Signal(max=ratio)
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counter_ce = Signal()
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counter_reset = Signal()
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self.sync += \
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If(counter_reset,
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counter.eq(0)
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).Elif(counter_ce,
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counter.eq(counter + 1)
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)
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counter_offset = Signal(max=ratio)
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counter_done = Signal()
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self.comb += [
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counter_offset.eq(address.q),
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counter_done.eq((counter + counter_offset) == ratio-1)
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]
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cached_data = Signal(dw_to)
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cached_sel = Signal(dw_to//8)
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end_of_burst = Signal()
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self.comb += end_of_burst.eq(~master.cyc |
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(master.stb & master.cyc & master.ack & ((master.cti == 7) | counter_done)))
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need_refill = FlipFlop(reset=1)
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self.submodules += need_refill
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self.comb += [
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need_refill.reset.eq(end_of_burst),
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need_refill.d.eq(0)
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]
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# Main FSM
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self.submodules.fsm = fsm = FSM()
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fsm.act("IDLE",
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counter_reset.eq(1),
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If(master.stb & master.cyc,
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address.ce.eq(1),
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If(master.we,
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NextState("WRITE")
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).Else(
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If(need_refill.q,
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NextState("REFILL")
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).Else(
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NextState("READ")
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)
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)
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)
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)
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fsm.act("WRITE",
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If(master.stb & master.cyc,
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write.eq(1),
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counter_ce.eq(1),
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master.ack.eq(1),
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If(counter_done,
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NextState("EVICT")
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)
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).Elif(~master.cyc,
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NextState("EVICT")
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)
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)
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fsm.act("EVICT",
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evict.eq(1),
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slave.stb.eq(1),
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slave.we.eq(1),
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slave.cyc.eq(1),
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slave.dat_w.eq(cached_data),
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slave.sel.eq(cached_sel),
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If(slave.ack,
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NextState("IDLE")
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)
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)
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fsm.act("REFILL",
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refill.eq(1),
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slave.stb.eq(1),
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slave.cyc.eq(1),
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If(slave.ack,
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need_refill.ce.eq(1),
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NextState("READ")
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)
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)
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fsm.act("READ",
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read.eq(1),
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If(master.stb & master.cyc,
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master.ack.eq(1)
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),
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NextState("IDLE")
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)
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# Address
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self.comb += [
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slave.cti.eq(7), # we are not able to generate bursts since up-converting
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slave.adr.eq(address.q[ratiobits:])
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]
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# Datapath
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cached_datas = [FlipFlop(dw_from) for i in range(ratio)]
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cached_sels = [FlipFlop(dw_from//8) for i in range(ratio)]
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self.submodules += cached_datas, cached_sels
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cases = {}
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for i in range(ratio):
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write_sel = Signal()
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cases[i] = write_sel.eq(1)
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self.comb += [
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cached_sels[i].reset.eq(counter_reset),
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If(write,
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cached_datas[i].d.eq(master.dat_w),
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).Else(
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cached_datas[i].d.eq(slave.dat_r[dw_from*i:dw_from*(i+1)])
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),
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cached_sels[i].d.eq(master.sel),
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If((write & write_sel) | refill,
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cached_datas[i].ce.eq(1),
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cached_sels[i].ce.eq(1)
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)
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]
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self.comb += Case(counter + counter_offset, cases)
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cases = {}
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for i in range(ratio):
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cases[i] = master.dat_r.eq(cached_datas[i].q)
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self.comb += Case(address.q[:ratiobits], cases)
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self.comb += [
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cached_data.eq(Cat([cached_data.q for cached_data in cached_datas])),
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cached_sel.eq(Cat([cached_sel.q for cached_sel in cached_sels]))
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]
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class Converter(Module):
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class Converter(Module):
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"""Converter
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"""Converter
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@ -513,8 +339,7 @@ class Converter(Module):
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downconverter = DownConverter(master, slave)
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downconverter = DownConverter(master, slave)
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self.submodules += downconverter
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self.submodules += downconverter
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elif dw_from < dw_to:
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elif dw_from < dw_to:
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upconverter = UpConverter(master, slave)
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raise NotImplementedError
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self.submodules += upconverter
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else:
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else:
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self.comb += master.connect(slave)
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self.comb += master.connect(slave)
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